oota-llvm.git
12 years agoRemove code in MipsAsmPrinter and MipsMCInstLower.
Akira Hatanaka [Thu, 14 Jun 2012 01:20:12 +0000 (01:20 +0000)]
Remove code in MipsAsmPrinter and MipsMCInstLower.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158434 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd long branch expansion pass for MIPS.
Akira Hatanaka [Thu, 14 Jun 2012 01:19:35 +0000 (01:19 +0000)]
Add long branch expansion pass for MIPS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158433 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd AT to the list of registers clobbered by branches so that it is available
Akira Hatanaka [Thu, 14 Jun 2012 01:17:59 +0000 (01:17 +0000)]
Add AT to the list of registers clobbered by branches so that it is available
as a scratch register when they are expanded to long branches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158432 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoIn MipsRegisterInfo::eliminateFrameIndex, call Mips::loadImmediate
Akira Hatanaka [Thu, 14 Jun 2012 01:17:36 +0000 (01:17 +0000)]
In MipsRegisterInfo::eliminateFrameIndex, call Mips::loadImmediate
to load an immediate that does not fit into 16-bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158431 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoIn MipsFrameLowering::emitPrologue and emitEpilogue, call Mips::loadImmediate
Akira Hatanaka [Thu, 14 Jun 2012 01:17:13 +0000 (01:17 +0000)]
In MipsFrameLowering::emitPrologue and emitEpilogue, call Mips::loadImmediate
to load an immediate that does not fit into 16-bit. Also, take into
consideration the global base register slot on the stack when computing the
stack size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158430 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoDefine function MipsInstrInfo::GetInstSizeInBytes, which will be called to
Akira Hatanaka [Thu, 14 Jun 2012 01:16:45 +0000 (01:16 +0000)]
Define function MipsInstrInfo::GetInstSizeInBytes, which will be called to
compute the size of basic blocks in a function. Also, define a function which
emits a series of instructions to load an immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158429 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoIn MipsISelDAGToDAG.cpp, store the global base register to a stack frame object.
Akira Hatanaka [Thu, 14 Jun 2012 01:16:15 +0000 (01:16 +0000)]
In MipsISelDAGToDAG.cpp, store the global base register to a stack frame object.
Long-branches need access to the global base register to get the destination
address.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158428 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd methods to MipsFunctionInfo for initializing and accessing the stack frame
Akira Hatanaka [Thu, 14 Jun 2012 01:15:36 +0000 (01:15 +0000)]
Add methods to MipsFunctionInfo for initializing and accessing the stack frame
object for the global base register.

This is the first of a series of patches which implements long branch expansion
for MIPS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158427 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoBundle jump/branch instructions with the instructions in the delay slot in
Akira Hatanaka [Wed, 13 Jun 2012 23:25:52 +0000 (23:25 +0000)]
Bundle jump/branch instructions with the instructions in the delay slot in
delay slot filler pass of MIPS, per suggestion of Jakob Stoklund Olesen.

This change, along with the fix in r158154, enables machine verification
to be run after delay slot filling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158426 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoGroup the 'unsigned' members after the pointer to avoid 4 bytes of
Chandler Carruth [Wed, 13 Jun 2012 21:44:07 +0000 (21:44 +0000)]
Group the 'unsigned' members after the pointer to avoid 4 bytes of
padding on x86-64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158421 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoImplement a DAGCombine in MipsISelLowering.cpp which transforms the following
Akira Hatanaka [Wed, 13 Jun 2012 20:33:18 +0000 (20:33 +0000)]
Implement a DAGCombine in MipsISelLowering.cpp which transforms the following
pattern:

(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))

"tjt" is a TargetJumpTable node.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158419 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSet a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp.
Akira Hatanaka [Wed, 13 Jun 2012 19:33:32 +0000 (19:33 +0000)]
Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158414 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSimplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp.
Akira Hatanaka [Wed, 13 Jun 2012 19:06:08 +0000 (19:06 +0000)]
Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158413 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoImplement fastcc calling convention for MIPS.
Akira Hatanaka [Wed, 13 Jun 2012 18:06:00 +0000 (18:06 +0000)]
Implement fastcc calling convention for MIPS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158410 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix pattern for MKMSK instruction.
Richard Osborne [Wed, 13 Jun 2012 17:59:12 +0000 (17:59 +0000)]
Fix pattern for MKMSK instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158409 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRevert "Allow SROA to look at a vector type and see if the offset is out of range...
Pete Cooper [Wed, 13 Jun 2012 17:55:22 +0000 (17:55 +0000)]
Revert "Allow SROA to look at a vector type and see if the offset is out of range to be replaced with a scalar access"

This reverts commit 51786e0aaec76b973205066bd44f7f427b21969f.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158408 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAllow SROA to look at a vector type and see if the offset is out of range to be repla...
Pete Cooper [Wed, 13 Jun 2012 17:30:34 +0000 (17:30 +0000)]
Allow SROA to look at a vector type and see if the offset is out of range to be replaced with a scalar access

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158407 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix building ThreadLocal.cpp with --disable-threads.
Argyrios Kyrtzidis [Wed, 13 Jun 2012 16:30:06 +0000 (16:30 +0000)]
Fix building ThreadLocal.cpp with --disable-threads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158405 91177308-0d34-0410-b5e6-96231b3b80d8

12 years ago*typo: Cyles changed to Cycles
Kay Tiong Khoo [Wed, 13 Jun 2012 15:53:04 +0000 (15:53 +0000)]
*typo: Cyles changed to Cycles

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158404 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse LTO_CODEGEN_PIC_MODEL_DYNAMIC for PIE. This requirest a git version of
Rafael Espindola [Wed, 13 Jun 2012 13:30:24 +0000 (13:30 +0000)]
Use LTO_CODEGEN_PIC_MODEL_DYNAMIC for PIE. This requirest a git version of
gold to work. Since the enum value LDPO_PIE has just been added to plugin-api.h,
use a numeric constant for now so that we don't require an unreleased
version of gold to build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158402 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoIt is possible for several constants which aren't individually absorbing to
Duncan Sands [Wed, 13 Jun 2012 12:15:56 +0000 (12:15 +0000)]
It is possible for several constants which aren't individually absorbing to
combine to the absorbing element.  Thanks to nbjoerg on IRC for pointing this
out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158399 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoWhen linearizing a multiplication, return at once if we see a factor of zero,
Duncan Sands [Wed, 13 Jun 2012 09:42:13 +0000 (09:42 +0000)]
When linearizing a multiplication, return at once if we see a factor of zero,
since then the entire expression must equal zero (similarly for other operations
with an absorbing element).  With this in place a bunch of reassociate code for
handling constants is dead since it is all taken care of when linearizing.  No
intended functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158398 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix intrinsics for XOP frczss/sd instructions. These instructions only take one sourc...
Craig Topper [Wed, 13 Jun 2012 07:18:53 +0000 (07:18 +0000)]
Fix intrinsics for XOP frczss/sd instructions. These instructions only take one source register and zero the upper bits of the destination rather than preserving them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158396 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd another missing 64-bit itinerary definition for the PPC A2 core.
Hal Finkel [Wed, 13 Jun 2012 05:55:09 +0000 (05:55 +0000)]
Add another missing 64-bit itinerary definition for the PPC A2 core.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158393 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSimplifyCFG: fold unconditional branch to its predecessor if profitable.
Manman Ren [Wed, 13 Jun 2012 05:43:29 +0000 (05:43 +0000)]
SimplifyCFG: fold unconditional branch to its predecessor if profitable.

This patch extends FoldBranchToCommonDest to fold unconditional branches.
For unconditional branches, we fold them if it is easy to update the phi nodes
in the common successors.

rdar://10554090

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158392 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEliminate struct TableGenBackend.
Jakob Stoklund Olesen [Wed, 13 Jun 2012 05:15:49 +0000 (05:15 +0000)]
Eliminate struct TableGenBackend.

TableGen backends are simply written as functions now.

Patch by Sean Silva!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158389 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoClean up trailing blanks in Mips16InstrFormats.td
Akira Hatanaka [Wed, 13 Jun 2012 02:42:47 +0000 (02:42 +0000)]
Clean up trailing blanks in Mips16InstrFormats.td

Patch by Reed Kotler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158382 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agodisable use of directive .set nomicromips
Akira Hatanaka [Wed, 13 Jun 2012 02:41:14 +0000 (02:41 +0000)]
disable use of directive .set nomicromips
until this directive is pushed in gas to open source fsf

Patch by Reed Kotler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158381 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agosched: fix latency of memory dependence chain edges for consistency.
Andrew Trick [Wed, 13 Jun 2012 02:39:03 +0000 (02:39 +0000)]
sched: fix latency of memory dependence chain edges for consistency.

For store->load dependencies that may alias, we should always use
TrueMemOrderLatency, which may eventually become a subtarget hook. In
effect, we should guarantee at least TrueMemOrderLatency on at least
one DAG path from a store to a may-alias load.

This should fix the standard mode as well as -enable-aa-sched-mi".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158380 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agosched: Avoid trivially redundant DAG edges. Take the one with higher latency.
Andrew Trick [Wed, 13 Jun 2012 02:39:00 +0000 (02:39 +0000)]
sched: Avoid trivially redundant DAG edges. Take the one with higher latency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158379 91177308-0d34-0410-b5e6-96231b3b80d8

12 years ago1. fix places where immed is used in place of imm to be consistent with
Akira Hatanaka [Wed, 13 Jun 2012 02:37:54 +0000 (02:37 +0000)]
1. fix places where immed is used in place of imm to be consistent with
non mips16
2. fix some comments to change OPcode->EXTEND for extended instructions

Patch by Reed Kotler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158378 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd some missing 64-bit itinerary definitions for the PPC A2 core.
Hal Finkel [Tue, 12 Jun 2012 20:32:29 +0000 (20:32 +0000)]
Add some missing 64-bit itinerary definitions for the PPC A2 core.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158373 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse DenseMap as SmallMap workaround rather than std::map, at Chandler's request.
Duncan Sands [Tue, 12 Jun 2012 20:26:43 +0000 (20:26 +0000)]
Use DenseMap as SmallMap workaround rather than std::map, at Chandler's request.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158371 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse std::map rather than SmallMap because SmallMap assumes that the value has
Duncan Sands [Tue, 12 Jun 2012 20:16:51 +0000 (20:16 +0000)]
Use std::map rather than SmallMap because SmallMap assumes that the value has
POD type, causing memory corruption when mapping to APInts with bitwidth > 64.
Merge another crash testcase into crash.ll while there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158369 91177308-0d34-0410-b5e6-96231b3b80d8

12 years ago[arm-fast-isel] Add support for -arm-long-calls.
Chad Rosier [Tue, 12 Jun 2012 19:25:13 +0000 (19:25 +0000)]
[arm-fast-isel] Add support for -arm-long-calls.
Patch by Jush Lu <jush.msn@gmail.com>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158368 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSplit out the PPC instruction class IntSimple from IntGeneral.
Hal Finkel [Tue, 12 Jun 2012 19:01:24 +0000 (19:01 +0000)]
Split out the PPC instruction class IntSimple from IntGeneral.

On the POWER7, adds and logical operations can also be handled
in the load/store pipelines. We'll call these IntSimple.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158366 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRemove use of GNU extension to resolve Clang warning.
David Blaikie [Tue, 12 Jun 2012 17:06:32 +0000 (17:06 +0000)]
Remove use of GNU extension to resolve Clang warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158364 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFixes for PPC host detection and features.
Hal Finkel [Tue, 12 Jun 2012 16:39:23 +0000 (16:39 +0000)]
Fixes for PPC host detection and features.

POWER4 is a 64-bit CPU (better matched to the 970).
The g3 is really the 750 (no altivec), the g4+ is the 74xx (not the 750).

Patch by Andreas Tobler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158363 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse correct syntax highliter in code blocks. Noticed by Sean Silva.
Dmitri Gribenko [Tue, 12 Jun 2012 15:45:07 +0000 (15:45 +0000)]
Use correct syntax highliter in code blocks.  Noticed by Sean Silva.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158359 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoNow that Reassociate's LinearizeExprTree can look through arbitrary expression
Duncan Sands [Tue, 12 Jun 2012 14:33:56 +0000 (14:33 +0000)]
Now that Reassociate's LinearizeExprTree can look through arbitrary expression
topologies, it is quite possible for a leaf node to have huge multiplicity, for
example: x0 = x*x, x1 = x0*x0, x2 = x1*x1, ... rapidly gives a value which is x
raised to a vast power (the multiplicity, or weight, of x).  This patch fixes
the computation of weights by correctly computing them no matter how big they
are, rather than just overflowing and getting a wrong value.  It turns out that
the weight for a value never needs more bits to represent than the value itself,
so it is enough to represent weights as APInts of the same bitwidth and do the
right overflow-avoiding dance steps when computing weights.  As a side-effect it
reduces the number of multiplies needed in some cases of large powers.  While
there, in view of external uses (eg by the vectorizer) I made LinearizeExprTree
static, pushing the rank computation out into users.  This is progress towards
fixing PR13021.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158358 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd two newlines in ParseSubtargetFeatures's debug output after the CPU is printed.
Hal Finkel [Tue, 12 Jun 2012 04:21:36 +0000 (04:21 +0000)]
Add two newlines in ParseSubtargetFeatures's debug output after the CPU is printed.

There is otherwise not a newline between the CPU name and the start of the next
pass's output which makes both difficult to read.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158350 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoReapply r158337, this time properly protect Darwin/PPC host CPU use with __ppc__.
Hal Finkel [Tue, 12 Jun 2012 03:03:13 +0000 (03:03 +0000)]
Reapply r158337, this time properly protect Darwin/PPC host CPU use with __ppc__.

Original commit message:
Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName().

Both the new Linux functionality and the old Darwin functions have been moved.
This change also allows this information to be queried directly by clang and
other frontends (clang, for example, will now have real -mcpu=native support).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158349 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSatisfy C++ aliasing rules, per suggestion by Chandler.
Argyrios Kyrtzidis [Tue, 12 Jun 2012 01:06:16 +0000 (01:06 +0000)]
Satisfy C++ aliasing rules, per suggestion by Chandler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158346 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRevert r158337 "Move PPC host-CPU detection logic from PPCSubtarget into sys::getHost...
Jakob Stoklund Olesen [Tue, 12 Jun 2012 00:58:40 +0000 (00:58 +0000)]
Revert r158337 "Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName()."

This commit broke most of the PowerPC unit tests when running on
Intel/Apple.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158345 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFileCheck docs: remove leftover HTML markup.
Dmitri Gribenko [Tue, 12 Jun 2012 00:48:47 +0000 (00:48 +0000)]
FileCheck docs: remove leftover HTML markup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158344 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFor llvm::sys::ThreadLocalImpl instead of malloc'ing the platform-specific
Argyrios Kyrtzidis [Tue, 12 Jun 2012 00:21:31 +0000 (00:21 +0000)]
For llvm::sys::ThreadLocalImpl instead of malloc'ing the platform-specific
thread local data, embed them in the class using a uint64_t and make sure
we get compiler errors if there's a platform where this is not big enough.

This makes ThreadLocal more safe for using it in conjunction with CrashRecoveryContext.

Related to crash in rdar://11434201.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158342 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agomisched: When querying RegisterPressureTracker, always save current and max pressure.
Andrew Trick [Mon, 11 Jun 2012 23:42:23 +0000 (23:42 +0000)]
misched: When querying RegisterPressureTracker, always save current and max pressure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158340 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agomisched: regpressure getMaxPressureDelta, revert accidental checkin.
Andrew Trick [Mon, 11 Jun 2012 23:42:20 +0000 (23:42 +0000)]
misched: regpressure getMaxPressureDelta, revert accidental checkin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158339 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMove PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName().
Hal Finkel [Mon, 11 Jun 2012 23:14:31 +0000 (23:14 +0000)]
Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName().

Both the new Linux functionality and the old Darwin functions have been moved.
This change also allows this information to be queried directly by clang and
other frontends (clang, for example, will now have real -mcpu=native support).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158337 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix test that depends on register allocation.
Jakob Stoklund Olesen [Mon, 11 Jun 2012 21:14:28 +0000 (21:14 +0000)]
Fix test that depends on register allocation.

The test is really checking the prolog/epilog load/store multiple
formation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158328 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEnable MFOCRF generation on the PPC A2 core.
Hal Finkel [Mon, 11 Jun 2012 19:57:04 +0000 (19:57 +0000)]
Enable MFOCRF generation on the PPC A2 core.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158324 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRename the PPC target feature gpul to mfocrf.
Hal Finkel [Mon, 11 Jun 2012 19:57:01 +0000 (19:57 +0000)]
Rename the PPC target feature gpul to mfocrf.

The PPC target feature gpul (IsGigaProcessor) was only used for one thing:
To enable the generation of the MFOCRF instruction. Furthermore, this
instruction is available on other PPC cores outside of the G5 line. This
feature now corresponds to the HasMFOCRF flag.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158323 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd A2 to the list of PPC CPUs recognized by Linux host CPU-type detection.
Hal Finkel [Mon, 11 Jun 2012 19:56:57 +0000 (19:56 +0000)]
Add A2 to the list of PPC CPUs recognized by Linux host CPU-type detection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158322 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix test case to work on ARM.
Jakob Stoklund Olesen [Mon, 11 Jun 2012 16:01:14 +0000 (16:01 +0000)]
Fix test case to work on ARM.

Patch by James Benton!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158316 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEmit the two-operand form of the PPC mfcr instruction as mfocrf.
Hal Finkel [Mon, 11 Jun 2012 15:43:15 +0000 (15:43 +0000)]
Emit the two-operand form of the PPC mfcr instruction as mfocrf.

This is necessary on Linux and supported on Darwin, see PR2604.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158315 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd local CPU detection for Linux PPC.
Hal Finkel [Mon, 11 Jun 2012 15:43:13 +0000 (15:43 +0000)]
Add local CPU detection for Linux PPC.

This functionality mirrors that available on PPC/Darwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158314 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd POWER6 and POWER7 CPU types to the PPC backend.
Hal Finkel [Mon, 11 Jun 2012 15:43:08 +0000 (15:43 +0000)]
Add POWER6 and POWER7 CPU types to the PPC backend.

No functional change; these will be used by upcoming scheduler enhancements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158313 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoWrite llvm-tblgen backends as functions instead of sub-classes.
Jakob Stoklund Olesen [Mon, 11 Jun 2012 15:37:55 +0000 (15:37 +0000)]
Write llvm-tblgen backends as functions instead of sub-classes.

The TableGenBackend base class doesn't do much, and will be removed
completely soon.

Patch by Sean Silva!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158311 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix a problem with the reverse bundle iterators.
Jakob Stoklund Olesen [Mon, 11 Jun 2012 15:11:12 +0000 (15:11 +0000)]
Fix a problem with the reverse bundle iterators.

This showed up the first time rend() was called on a bundled instruction
in the Mips backend.

Also avoid dereferencing end() in bundle_iterator::operator++().

We still don't have a place to put unit tests for this stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158310 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoObject file output from llc isn't experimental anymore.
Benjamin Kramer [Mon, 11 Jun 2012 09:40:10 +0000 (09:40 +0000)]
Object file output from llc isn't experimental anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158305 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRe-enable the CMN instruction.
Bill Wendling [Mon, 11 Jun 2012 08:07:26 +0000 (08:07 +0000)]
Re-enable the CMN instruction.

We turned off the CMN instruction because it had semantics which we weren't
getting correct. If we are comparing with an immediate, then it's okay to use
the CMN instruction.
<rdar://problem/7569620>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158302 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoInstCombine: factor code better.
Benjamin Kramer [Mon, 11 Jun 2012 08:01:25 +0000 (08:01 +0000)]
InstCombine: factor code better.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158301 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoInstCombine: Turn (zext A) == (B & (1<<X)-1) into A == (trunc B), narrowing the compare.
Benjamin Kramer [Sun, 10 Jun 2012 20:35:00 +0000 (20:35 +0000)]
InstCombine: Turn (zext A) == (B & (1<<X)-1) into A == (trunc B), narrowing the compare.

This saves a cast, and zext is more expensive on platforms with subreg support
than trunc is. This occurs in the BSD implementation of memchr(3), see PR12750.
On the synthetic benchmark from that bug stupid_memchr and bsd_memchr have the
same performance now when not inlining either function.

stupid_memchr: 323.0us
bsd_memchr: 321.0us
memchr: 479.0us

where memchr is the llvm-gcc compiled bsd_memchr from osx lion's libc. When
inlining is enabled bsd_memchr still regresses down to llvm-gcc memchr time,
I haven't fully understood the issue yet, something is grossly mangling the
loop after inlining.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158297 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEnable ILP scheduling for all nodes by default on PPC.
Hal Finkel [Sun, 10 Jun 2012 19:32:29 +0000 (19:32 +0000)]
Enable ILP scheduling for all nodes by default on PPC.

Over the entire test-suite, this has an insignificantly negative average
performance impact, but reduces some of the worst slowdowns from the
anti-dep. change (r158294).

Largest speedups:
SingleSource/Benchmarks/Stanford/Quicksort - 28%
SingleSource/Benchmarks/Stanford/Towers - 24%
SingleSource/Benchmarks/Shootout-C++/matrix - 23%
MultiSource/Benchmarks/SciMark2-C/scimark2 - 19%
MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - 15%
(matrix and automotive-bitcount were both in the top-5 slowdown list from the
anti-dep. change)

Largest slowdowns:
MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 28%
MultiSource/Benchmarks/mediabench/gsm/toast/toast - 26%
MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan - 21%
SingleSource/Benchmarks/CoyoteBench/lpbench - 20%
MultiSource/Applications/d/make_dparser - 16%

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158296 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd AutoUpgrade support for the SSE4 ptest intrinsics.
Nadav Rotem [Sun, 10 Jun 2012 18:42:51 +0000 (18:42 +0000)]
Add AutoUpgrade support for the SSE4 ptest intrinsics.
Patch by Michael Kuperstein.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158295 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse critical anti-dep. breaking on all PPC targets, but also add other register classes.
Hal Finkel [Sun, 10 Jun 2012 11:15:36 +0000 (11:15 +0000)]
Use critical anti-dep. breaking on all PPC targets, but also add other register classes.

Using 'all' instead of 'critical' would be better because it would make it easier to
satisfy the bundling constraints, but, as noted in the FIXME, that is currently not
possible with the crs.

This yields an average 1% speedup over the entire test suite (on Power 7). Largest speedups:
SingleSource/Benchmarks/Shootout-C++/moments - 40%
MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 28%
SingleSource/Benchmarks/BenchmarkGame/nsieve-bits - 26%
SingleSource/Benchmarks/McGill/misr - 23%
MultiSource/Applications/JM/ldecod/ldecod - 22%

Largest slowdowns:
SingleSource/Benchmarks/Shootout-C++/matrix - -29%
SingleSource/Benchmarks/Shootout-C++/ary3 - -22%
MultiSource/Benchmarks/BitBench/uuencode/uuencode - -18%
SingleSource/Benchmarks/Shootout-C++/ary - -17%
MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - -15%

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158294 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd intrinsics for immediate form of XOP vprot instructions. Use i128mem instead...
Craig Topper [Sun, 10 Jun 2012 07:31:56 +0000 (07:31 +0000)]
Add intrinsics for immediate form of XOP vprot instructions. Use i128mem instead of f128mem for integer XOP instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158291 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoImprove ext/trunc patterns on PPC64.
Hal Finkel [Sat, 9 Jun 2012 22:10:19 +0000 (22:10 +0000)]
Improve ext/trunc patterns on PPC64.

The PPC64 backend had patterns for i32 <-> i64 extensions and truncations that
would leave self-moves in the final assembly. Replacing those patterns with ones
based on the SUBREG builtins yields better-looking code.

Thanks to Jakob and Owen for their suggestions in this matter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158283 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse XOP vpcom intrinsics in patterns instead of a target specific SDNode type. Remove...
Craig Topper [Sat, 9 Jun 2012 17:02:24 +0000 (17:02 +0000)]
Use XOP vpcom intrinsics in patterns instead of a target specific SDNode type. Remove the custom lowering code that selected the SDNode type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158279 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoReplace XOP vpcom intrinsics with fewer intrinsics that take the immediate as an...
Craig Topper [Sat, 9 Jun 2012 16:46:13 +0000 (16:46 +0000)]
Replace XOP vpcom intrinsics with fewer intrinsics that take the immediate as an argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158278 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoHashing: Remove outdated comment. Support for reserved hash values was removed in...
Benjamin Kramer [Sat, 9 Jun 2012 15:33:28 +0000 (15:33 +0000)]
Hashing: Remove outdated comment. Support for reserved hash values was removed in r151865.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158276 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoDisabling a spurious deprecation warning about using PathV1 from within the PathV1...
Aaron Ballman [Sat, 9 Jun 2012 13:59:29 +0000 (13:59 +0000)]
Disabling a spurious deprecation warning about using PathV1 from within the PathV1 implementation file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158274 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFixing a typo in the comments.
Aaron Ballman [Sat, 9 Jun 2012 13:46:36 +0000 (13:46 +0000)]
Fixing a typo in the comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158273 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAllocate the contents of DwarfDebug's StringMaps in a single big BumpPtrAllocator.
Benjamin Kramer [Sat, 9 Jun 2012 10:34:15 +0000 (10:34 +0000)]
Allocate the contents of DwarfDebug's StringMaps in a single big BumpPtrAllocator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158265 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSilence a gcc-4.6 warning: GCC fails to understand that secondReg and cmpOp2 are
Duncan Sands [Sat, 9 Jun 2012 10:04:03 +0000 (10:04 +0000)]
Silence a gcc-4.6 warning: GCC fails to understand that secondReg and cmpOp2 are
correlated, and thinks that cmpOp2 may be used uninitialized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158263 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEnable tail merging on PPC.
Hal Finkel [Sat, 9 Jun 2012 03:14:50 +0000 (03:14 +0000)]
Enable tail merging on PPC.

Tail merging had been disabled on PPC because it would disturb bundling decisions
made during pre-RA scheduling on the 970 cores. Now, however, all bundling decisions
are made during post-RA scheduling, and tail merging is generally beneficial (the
average test-suite speedup is insignificantly positive).

Largest test-suite speedups:
MultiSource/Benchmarks/mediabench/gsm/toast/toast - 30%
MultiSource/Benchmarks/BitBench/uuencode/uuencode - 23%
SingleSource/Benchmarks/Shootout-C++/ary - 21%
SingleSource/Benchmarks/Stanford/Queens - 17%

Largest slowdowns:
MultiSource/Benchmarks/MiBench/security-sha/security-sha - 24%
MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 22%
MultiSource/Applications/JM/ldecod/ldecod - 14%
MultiSource/Benchmarks/mediabench/g721/g721encode/encode - 9%

This is improved by using full (instead of just critical) anti-dependency breaking,
but doing so still causes miscompiles and so cannot yet be enabled by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158259 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRegister pressure: added getPressureAfterInstr.
Andrew Trick [Sat, 9 Jun 2012 02:16:58 +0000 (02:16 +0000)]
Register pressure: added getPressureAfterInstr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158256 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSketch a LiveRegMatrix analysis pass.
Jakob Stoklund Olesen [Sat, 9 Jun 2012 02:13:10 +0000 (02:13 +0000)]
Sketch a LiveRegMatrix analysis pass.

The LiveRegMatrix represents the live range of assigned virtual
registers in a Live interval union per register unit. This is not
fundamentally different from the interference tracking in RegAllocBase
that both RABasic and RAGreedy use.

The important differences are:

- LiveRegMatrix tracks interference per register unit instead of per
  physical register. This makes interference checks cheaper and
  assignments slightly more expensive. For example, the ARM D7 reigster
  has 24 aliases, so we would check 24 physregs before assigning to one.
  With unit-based interference, we check 2 units before assigning to 2
  units.

- LiveRegMatrix caches regmask interference checks. That is currently
  duplicated functionality in RABasic and RAGreedy.

- LiveRegMatrix is a pass which makes it possible to insert
  target-dependent passes between register allocation and rewriting.
  Such passes could tweak the register assignments with interference
  checking support from LiveRegMatrix.

Eventually, RABasic and RAGreedy will be switched to LiveRegMatrix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158255 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTest commit
Jack Carter [Sat, 9 Jun 2012 00:27:55 +0000 (00:27 +0000)]
Test commit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158250 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAlso compute MBB live-in lists in the new rewriter pass.
Jakob Stoklund Olesen [Sat, 9 Jun 2012 00:14:47 +0000 (00:14 +0000)]
Also compute MBB live-in lists in the new rewriter pass.

This deduplicates some code from the optimizing register allocators, and
it means that it is now possible to change the register allocators'
solutions simply by editing the VirtRegMap between the register
allocator pass and the rewriter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158249 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoConvert comments to proper Doxygen comments.
Dmitri Gribenko [Sat, 9 Jun 2012 00:01:45 +0000 (00:01 +0000)]
Convert comments to proper Doxygen comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158248 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRemoving strange "using" declarations form TargetInstrInfo.
Andrew Trick [Fri, 8 Jun 2012 23:56:26 +0000 (23:56 +0000)]
Removing strange "using" declarations form TargetInstrInfo.

I can't imagine why these were added. Trial and error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158247 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoReintroduce VirtRegRewriter.
Jakob Stoklund Olesen [Fri, 8 Jun 2012 23:44:45 +0000 (23:44 +0000)]
Reintroduce VirtRegRewriter.

OK, not really. We don't want to reintroduce the old rewriter hacks.

This patch extracts virtual register rewriting as a separate pass that
runs after the register allocator. This is possible now that
CodeGen/Passes.cpp can configure the full optimizing register allocator
pipeline.

The rewriter pass uses register assignments in VirtRegMap to rewrite
virtual registers to physical registers, and it inserts kill flags based
on live intervals.

These finalization steps are the same for the optimizing register
allocators: RABasic, RAGreedy, and PBQP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158244 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoDon't run RAFast in the optimizing regalloc pipeline.
Jakob Stoklund Olesen [Fri, 8 Jun 2012 23:15:12 +0000 (23:15 +0000)]
Don't run RAFast in the optimizing regalloc pipeline.

The fast register allocator is not supposed to work in the optimizing
pipeline. It doesn't make sense to compute live intervals, run full copy
coalescing, and then run RAFast.

Fast register allocation in the optimizing pipeline is better done by
RABasic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158242 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agocanonicalize:
Nuno Lopes [Fri, 8 Jun 2012 22:30:05 +0000 (22:30 +0000)]
canonicalize:
-%a + 42
into
42 - %a

previously we were emitting:
-(%a + 42)

This fixes the infinite loop in PR12338. The generated code is still not perfect, though.
Will work on that next

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158237 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoStart implementing pre-ra if-converter: using speculation and selects to eliminate...
Evan Cheng [Fri, 8 Jun 2012 21:53:50 +0000 (21:53 +0000)]
Start implementing pre-ra if-converter: using speculation and selects to eliminate branches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158234 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTargetInstrInfo hooks implemented in codegen should be declared pure virtual.
Andrew Trick [Fri, 8 Jun 2012 21:52:38 +0000 (21:52 +0000)]
TargetInstrInfo hooks implemented in codegen should be declared pure virtual.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158233 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoReapply commit 158073 with a fix (the testcase was already committed). The
Duncan Sands [Fri, 8 Jun 2012 20:15:33 +0000 (20:15 +0000)]
Reapply commit 158073 with a fix (the testcase was already committed).  The
problem was that by moving instructions around inside the function, the pass
could accidentally move the iterator being used to advance over the function
too.  Fix this by only processing the instruction equal to the iterator, and
leaving processing of instructions that might not be equal to the iterator
to later (later = after traversing the basic block; it could also wait until
after traversing the entire function, but this might make the sets quite big).
Original commit message:

Grab-bag of reassociate tweaks.  Unify handling of dead instructions and
instructions to reoptimize.  Exploit this to more systematically eliminate
dead instructions (this isn't very useful in practice but is convenient for
analysing some testcase I am working on).  No need for WeakVH any more: use
an AssertingVH instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158226 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRemove the TODO statement in the PPC README re: CTR loops
Hal Finkel [Fri, 8 Jun 2012 20:02:09 +0000 (20:02 +0000)]
Remove the TODO statement in the PPC README re: CTR loops

As Chris points out, this can now be removed!

TODO: check if the associated section on viterbi's inner loop can also be removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158224 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEnable PPC CTR loop formation by default.
Hal Finkel [Fri, 8 Jun 2012 19:19:53 +0000 (19:19 +0000)]
Enable PPC CTR loop formation by default.

Thanks to Jakob's help, this now causes no new test suite failures!

Over the entire test suite, this gives an average 1% speedup. The largest speedups are:
SingleSource/Benchmarks/Misc/pi - 108%
SingleSource/Benchmarks/CoyoteBench/lpbench - 54%
MultiSource/Benchmarks/Prolangs-C/unix-smail/unix-smail - 50%
SingleSource/Benchmarks/Shootout/ary3 - 32%
SingleSource/Benchmarks/Shootout-C++/matrix - 30%

The largest slowdowns are:
MultiSource/Benchmarks/mediabench/gsm/toast/toast - -30%
MultiSource/Benchmarks/Prolangs-C/bison/mybison - -25%
MultiSource/Benchmarks/BitBench/uuencode/uuencode - -22%
MultiSource/Applications/d/make_dparser - -14%
SingleSource/Benchmarks/Shootout-C++/ary - -13%

In light of these slowdowns, additional profiling work is obviously needed!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158223 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMark the PPC CTRRC and CTRRC8 register classes as non-allocatable.
Hal Finkel [Fri, 8 Jun 2012 19:02:08 +0000 (19:02 +0000)]
Mark the PPC CTRRC and CTRRC8 register classes as non-allocatable.

Marking these classes as non-alocatable allows CTR loop generation to
work correctly with the block placement passes, etc. These register
classes are currently used only by some unused TCRETURN patterns.
In future cleanup, these will be removed.

Thanks again to Jakob for suggesting this fix to the CTR loop problem!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158221 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEnable optimization for integer ABS on X86 if Subtarget has CMOV.
Manman Ren [Fri, 8 Jun 2012 18:58:26 +0000 (18:58 +0000)]
Enable optimization for integer ABS on X86 if Subtarget has CMOV.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158220 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTest case for r158160
Manman Ren [Fri, 8 Jun 2012 18:42:37 +0000 (18:42 +0000)]
Test case for r158160

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158218 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSched itinerary fix: Avoid static initializers.
Andrew Trick [Fri, 8 Jun 2012 18:25:47 +0000 (18:25 +0000)]
Sched itinerary fix: Avoid static initializers.

This fixes an accidental dependence on static initialization order that I introduced yesterday.

Thank you Lang!!!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158215 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix a crash in APInt::lshr when shiftAmt > BitWidth.
Chad Rosier [Fri, 8 Jun 2012 18:04:52 +0000 (18:04 +0000)]
Fix a crash in APInt::lshr when shiftAmt > BitWidth.
Patch by James Benton <jbenton@vmware.com>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158213 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix Target->Codegen dependence.
Andrew Trick [Fri, 8 Jun 2012 17:23:27 +0000 (17:23 +0000)]
Fix Target->Codegen dependence.

Bulk move of TargetInstrInfo implementation into
TargetInstrInfoImpl. This is dirty because the code isn't part of
TargetInstrInfoImpl class, nor should it be, because the methods are
not target hooks. However, it's the current mechanism for keeping
libTarget useful outside the backend. You'll get a not-so-nice link
error if you invoke a TargetInstrInfo method that depends on CodeGen.

The TargetInstrInfoImpl class should probably be removed since it
doesn't really solve this problem.

To really fix this, we probably need separate interfaces for the
CodeGen/nonCodeGen sides of TargetInstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158212 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoBoundsChecking: add support for ConstantPointerNull. fixes a bunch of instrumentation...
Nuno Lopes [Fri, 8 Jun 2012 16:31:42 +0000 (16:31 +0000)]
BoundsChecking: add support for ConstantPointerNull. fixes a bunch of instrumentation failures in loops with reallocs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158210 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agotest/CodeGen/Generic/APIntLoadStore.ll: Mark as XFAIL:ppc since r157911.
NAKAMURA Takumi [Fri, 8 Jun 2012 16:28:06 +0000 (16:28 +0000)]
test/CodeGen/Generic/APIntLoadStore.ll: Mark as XFAIL:ppc since r157911.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158209 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoDisable the PPC CTR-Loops pass by default.
Hal Finkel [Fri, 8 Jun 2012 15:38:25 +0000 (15:38 +0000)]
Disable the PPC CTR-Loops pass by default.

The pass itself works well, but the something in the Machine* infrastructure
does not understand terminators which define registers. Without the ability
to use the block-placement pass, etc. this causes performance regressions (and
so is turned off by default). Turning off the analysis turns off the problems
with the Machine* infrastructure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158206 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix a bug in the new PPC CTR-Loops pass.
Hal Finkel [Fri, 8 Jun 2012 15:38:23 +0000 (15:38 +0000)]
Fix a bug in the new PPC CTR-Loops pass.

The code which tests for an induction operation cannot assume that any
ADDI instruction will have a register operand because the operand could
also be a frame index; for example:
    %vreg16<def> = ADDI8 <fi#0>, 0; G8RC:%vreg16

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158205 91177308-0d34-0410-b5e6-96231b3b80d8