oota-llvm.git
11 years agoGenerate PPC early conditional returns
Hal Finkel [Mon, 8 Apr 2013 16:24:03 +0000 (16:24 +0000)]
Generate PPC early conditional returns

PowerPC has a conditional branch to the link register (return) instruction: BCLR.
This should be used any time when we'd otherwise have a conditional branch to a
return. This adds a small pass, PPCEarlyReturn, which runs just prior to the
branch selection pass (and, importantly, after block placement) to generate
these conditional returns when possible. It will also eliminate unconditional
branches to returns (these happen rarely; most of the time these have already
been tail duplicated by the time PPCEarlyReturn is invoked). This is a nice
optimization for small functions that do not maintain a stack frame.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179026 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDWARF parser: remove duplicated code and fix code style in DIE extractors.
Alexey Samsonov [Mon, 8 Apr 2013 14:37:16 +0000 (14:37 +0000)]
DWARF parser: remove duplicated code and fix code style in DIE extractors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179023 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd all 4 MachO object types. Use the stored type to implement is64Bits().
Rafael Espindola [Mon, 8 Apr 2013 13:25:33 +0000 (13:25 +0000)]
Add all 4 MachO object types. Use the stored type to implement is64Bits().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179021 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Control Flow support for pre EG gen
Vincent Lejeune [Mon, 8 Apr 2013 13:05:49 +0000 (13:05 +0000)]
R600: Control Flow support for pre EG gen

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179020 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSimplify the quoting here. Our lit emulator doesn't deal well with the
Chandler Carruth [Mon, 8 Apr 2013 10:07:50 +0000 (10:07 +0000)]
Simplify the quoting here. Our lit emulator doesn't deal well with the
nested quoting schemes, and they're not important here...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179014 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove a global 'endl' variable from the other file as well.
Chandler Carruth [Mon, 8 Apr 2013 08:55:18 +0000 (08:55 +0000)]
Remove a global 'endl' variable from the other file as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179010 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoClean up namespaces in obj2yaml.cpp.
Chandler Carruth [Mon, 8 Apr 2013 08:55:14 +0000 (08:55 +0000)]
Clean up namespaces in obj2yaml.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179009 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd ACLE link to ARM documentation sections
Tim Northover [Mon, 8 Apr 2013 08:42:24 +0000 (08:42 +0000)]
Add ACLE link to ARM documentation sections

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179006 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAArch64: remove barriers from AArch64 atomic operations.
Tim Northover [Mon, 8 Apr 2013 08:40:41 +0000 (08:40 +0000)]
AArch64: remove barriers from AArch64 atomic operations.

I've managed to convince myself that AArch64's acquire/release
instructions are sufficient to guarantee C++11's required semantics,
even in the sequentially-consistent case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179005 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoCleanup the formatting of obj2yaml.cpp.
Chandler Carruth [Mon, 8 Apr 2013 08:39:59 +0000 (08:39 +0000)]
Cleanup the formatting of obj2yaml.cpp.

I couldn't touch this file and not clean it up some. These reformattings
brought to you by clang-format, with some minor adjustments by me. More
spring cleaning to follow here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179004 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDon't define our own global 'endl' variable. While technically it had
Chandler Carruth [Mon, 8 Apr 2013 08:30:47 +0000 (08:30 +0000)]
Don't define our own global 'endl' variable. While technically it had
internal linkage and so wasn't a patent bug, it doesn't make any sense
here. We can avoid even calling operator<< by just embedding the newline
in the string literals that were already being streamed out. It also
gives the impression of some line-ending agnosticisms which is not
present, and that flushing happens when it doesn't.

If we want to use std::endl, we could do that, but honestly it doesn't
seem remotely worth it. Using '\n' directly is much more clear when
working with raw_ostream.

It also happens to fix builds with old crufty GCC STL implementations
that include std::endl into the global namespace (or headers written to
be compatible with such atrocities).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179003 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoARM: Remove unused variable.
Benjamin Kramer [Mon, 8 Apr 2013 08:07:35 +0000 (08:07 +0000)]
ARM: Remove unused variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179001 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoCleanup and improve PPC fsel generation
Hal Finkel [Sun, 7 Apr 2013 22:11:09 +0000 (22:11 +0000)]
Cleanup and improve PPC fsel generation

First, we should not cheat: fsel-based lowering of select_cc is a
finite-math-only optimization (the ISA manual, section F.3 of v2.06, makes
this clear, as does a note in our own README).

This also adds fsel-based lowering of EQ and NE condition codes. As it turned
out, fsel generation was covered by a grand total of zero regression test
cases. I've added some test cases to cover the existing behavior (which is now
finite-math only), as well as the new EQ cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179000 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoTargetLowering: Fix getTypeConversion handling of extended vector types
Arnold Schwaighofer [Sun, 7 Apr 2013 20:22:56 +0000 (20:22 +0000)]
TargetLowering: Fix getTypeConversion handling of extended vector types

The code in getTypeConversion attempts to promote the element vector type
before it trys to split or widen the vector.
After it failed finding a legal vector type by promoting it would continue using
the promoted vector element type. Thereby missing legal splitted vector types.
For example the type v32i32 that has a legal split of 4 x v3i32 on x86/sse2
would be transformed to: v32i256 and from there on successively split to:
v16i256, v8i256, v1i256 and then finally ends up as an i64 type.
By resetting the vector element type to the original vector element type that
existed before the promotion the code will attempt to split the vector type to
smaller vector widths of the same type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178999 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMake MachOObjectFile independent from MachOObject.
Rafael Espindola [Sun, 7 Apr 2013 20:01:29 +0000 (20:01 +0000)]
Make MachOObjectFile independent from MachOObject.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178998 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoImplement MachOObjectFile::getData directly.
Rafael Espindola [Sun, 7 Apr 2013 19:42:15 +0000 (19:42 +0000)]
Implement MachOObjectFile::getData directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178997 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoImplement MachOObjectFile::is64Bit directly.
Rafael Espindola [Sun, 7 Apr 2013 19:38:15 +0000 (19:38 +0000)]
Implement MachOObjectFile::is64Bit directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178996 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoImplement MachOObjectFile::getHeaderSize directly.
Rafael Espindola [Sun, 7 Apr 2013 19:31:49 +0000 (19:31 +0000)]
Implement MachOObjectFile::getHeaderSize directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178995 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoImplement MachOObjectFile::getHeader directly.
Rafael Espindola [Sun, 7 Apr 2013 19:26:57 +0000 (19:26 +0000)]
Implement MachOObjectFile::getHeader directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178994 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoImplement LowerCall_64 for the SPARC v9 64-bit ABI.
Jakob Stoklund Olesen [Sun, 7 Apr 2013 19:10:57 +0000 (19:10 +0000)]
Implement LowerCall_64 for the SPARC v9 64-bit ABI.

There is still no support for byval arguments (which I don't think are
needed) and varargs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178993 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoImplement MachOObjectFile::getHeaderSize and MachOObjectFile::getData.
Rafael Espindola [Sun, 7 Apr 2013 19:05:30 +0000 (19:05 +0000)]
Implement MachOObjectFile::getHeaderSize and MachOObjectFile::getData.

These were the last missing forwarding functions. Also consistently use
the forwarding functions instead of using MachOObj directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178992 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove LoadCommandInfo now that we always have a pointer to the command.
Rafael Espindola [Sun, 7 Apr 2013 18:42:06 +0000 (18:42 +0000)]
Remove LoadCommandInfo now that we always have a pointer to the command.

LoadCommandInfo was needed to keep a command and its offset in the file. Now
that we always have a pointer to the command, we don't need the offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178991 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd MachOObjectFile::LoadCommandInfo.
Rafael Espindola [Sun, 7 Apr 2013 18:08:12 +0000 (18:08 +0000)]
Add MachOObjectFile::LoadCommandInfo.

This avoids using MachOObject::getLoadCommandInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178990 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse getLoadCommandInfo instead of MachOObj->getLoadCommandInfo.
Rafael Espindola [Sun, 7 Apr 2013 17:41:59 +0000 (17:41 +0000)]
Use getLoadCommandInfo instead of MachOObj->getLoadCommandInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178989 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoConstruct MachOObject in MachOObjectFile's constructor.
Rafael Espindola [Sun, 7 Apr 2013 16:58:48 +0000 (16:58 +0000)]
Construct MachOObject in MachOObjectFile's constructor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178988 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove unused argument.
Rafael Espindola [Sun, 7 Apr 2013 16:40:00 +0000 (16:40 +0000)]
Remove unused argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178987 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove MachOObjectFile::getObject.
Rafael Espindola [Sun, 7 Apr 2013 16:07:35 +0000 (16:07 +0000)]
Remove MachOObjectFile::getObject.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178986 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove two uses of getObject.
Rafael Espindola [Sun, 7 Apr 2013 15:46:05 +0000 (15:46 +0000)]
Remove two uses of getObject.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178985 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove usage of InMemoryStruct in getSymbol.
Rafael Espindola [Sun, 7 Apr 2013 15:35:18 +0000 (15:35 +0000)]
Remove usage of InMemoryStruct in getSymbol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178984 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPPC Altivec load/store intrinsics can be marked IntrRead[Write]ArgMem
Hal Finkel [Sun, 7 Apr 2013 15:32:40 +0000 (15:32 +0000)]
PPC Altivec load/store intrinsics can be marked IntrRead[Write]ArgMem

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178983 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPPC rotate instructions don't have unmodeled side effcts
Hal Finkel [Sun, 7 Apr 2013 15:06:53 +0000 (15:06 +0000)]
PPC rotate instructions don't have unmodeled side effcts

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178982 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove a use of InMemoryStruct in llvm-readobj.
Rafael Espindola [Sun, 7 Apr 2013 15:05:12 +0000 (15:05 +0000)]
Remove a use of InMemoryStruct in llvm-readobj.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178981 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMake getObject const. Remove a const_cast.
Rafael Espindola [Sun, 7 Apr 2013 14:50:40 +0000 (14:50 +0000)]
Make getObject const. Remove a const_cast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178980 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove last use of InMemoryStruct in llvm-objdump.
Rafael Espindola [Sun, 7 Apr 2013 14:40:18 +0000 (14:40 +0000)]
Remove last use of InMemoryStruct in llvm-objdump.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178979 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMost PPC M[TF]CR instructions do not have side effects
Hal Finkel [Sun, 7 Apr 2013 14:33:13 +0000 (14:33 +0000)]
Most PPC M[TF]CR instructions do not have side effects

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178978 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove dead code.
Rafael Espindola [Sun, 7 Apr 2013 14:30:21 +0000 (14:30 +0000)]
Remove dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178977 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove unused argument.
Rafael Espindola [Sun, 7 Apr 2013 14:25:39 +0000 (14:25 +0000)]
Remove unused argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178976 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix PR15674 (and PR15603): a SROA think-o.
Chandler Carruth [Sun, 7 Apr 2013 11:47:54 +0000 (11:47 +0000)]
Fix PR15674 (and PR15603): a SROA think-o.

The fix for PR14972 in r177055 introduced a real think-o in the *store*
side, likely because I was much more focused on the load side. While we
can arbitrarily widen (or narrow) a loaded value, we can't arbitrarily
widen a value to be stored, as that changes the width of memory access!
Lock down the code path in the store rewriting which would do this to
only handle the intended circumstance.

All of the existing tests continue to pass, and I've added a test from
the PR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178974 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPPC pre-increment load instructions do not have side effects
Hal Finkel [Sun, 7 Apr 2013 06:30:47 +0000 (06:30 +0000)]
PPC pre-increment load instructions do not have side effects

A few were missed in r178972.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178973 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPPC pre-increment load instructions do not have side effects
Hal Finkel [Sun, 7 Apr 2013 05:46:58 +0000 (05:46 +0000)]
PPC pre-increment load instructions do not have side effects

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178972 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPPC MCRF instruction does not have side effects
Hal Finkel [Sun, 7 Apr 2013 05:16:57 +0000 (05:16 +0000)]
PPC MCRF instruction does not have side effects

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178971 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPPC FMR instruction does not have side effects
Hal Finkel [Sun, 7 Apr 2013 04:56:16 +0000 (04:56 +0000)]
PPC FMR instruction does not have side effects

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178970 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDW_FORM_sec_offset should be a relocation on platforms that use
Eric Christopher [Sun, 7 Apr 2013 03:43:09 +0000 (03:43 +0000)]
DW_FORM_sec_offset should be a relocation on platforms that use
a relocation across sections. Do this for DW_AT_stmt list in the
skeleton CU and check the relocations in the debug_info section.

Add a FIXME for multiple CUs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178969 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[cmake] Avoid rel+asserts warnings when passing -UNDEBUG
Reid Kleckner [Sun, 7 Apr 2013 01:45:01 +0000 (01:45 +0000)]
[cmake] Avoid rel+asserts warnings when passing -UNDEBUG

MSVC 2012 gives warning D9025, "overriding /D NDEBUG with -UNDEBUG".
Removing the original definition of NDEBUG silences this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178967 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoImplement LowerReturn_64 for SPARC v9.
Jakob Stoklund Olesen [Sat, 6 Apr 2013 23:57:33 +0000 (23:57 +0000)]
Implement LowerReturn_64 for SPARC v9.

Integer return values are sign or zero extended by the callee, and
structs up to 32 bytes in size can be returned in registers.

The CC_Sparc64 CallingConv definition is shared between
LowerFormalArguments_64 and LowerReturn_64. Function arguments and
return values are passed in the same registers.

The inreg flag is also used for return values. This is required to handle
C functions returning structs containing floats and ints:

  struct ifp {
    int i;
    float f;
  };

  struct ifp f(void);

LLVM IR:

  define inreg { i32, float } @f() {
     ...
     ret { i32, float } %retval
  }

The ABI requires that %retval.i is returned in the high bits of %i0
while %retval.f goes in %f1.

Without the inreg return value attribute, %retval.i would go in %i0 and
%retval.f would go in %f3 which is a more efficient way of returning
%multiple values, but it is not ABI compliant for returning C structs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178966 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSPARC v9 stack pointer bias.
Jakob Stoklund Olesen [Sat, 6 Apr 2013 21:38:57 +0000 (21:38 +0000)]
SPARC v9 stack pointer bias.

64-bit SPARC v9 processes use biased stack and frame pointers, so the
current function's stack frame is located at %sp+BIAS .. %fp+BIAS where
BIAS = 2047.

This makes more local variables directly accessible via [%fp+simm13]
addressing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178965 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoImplement PPCInstrInfo::FoldImmediate
Hal Finkel [Sat, 6 Apr 2013 19:30:30 +0000 (19:30 +0000)]
Implement PPCInstrInfo::FoldImmediate

There are certain PPC instructions into which we can fold a zero immediate
operand. We can detect such cases by looking at the register class required
by the using operand (so long as it is not otherwise constrained).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178961 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPPC ISEL is a select and never has side effects
Hal Finkel [Sat, 6 Apr 2013 19:30:28 +0000 (19:30 +0000)]
PPC ISEL is a select and never has side effects

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178960 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd a comment to TargetInstrInfo about FoldImmediate
Hal Finkel [Sat, 6 Apr 2013 19:30:20 +0000 (19:30 +0000)]
Add a comment to TargetInstrInfo about FoldImmediate

This comment documents the current behavior of the ARM implementation of this
callback, and also the soon-to-be-committed PPC version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178959 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoComplete formal arguments for the SPARC v9 64-bit ABI.
Jakob Stoklund Olesen [Sat, 6 Apr 2013 18:32:12 +0000 (18:32 +0000)]
Complete formal arguments for the SPARC v9 64-bit ABI.

All arguments are formally assigned to stack positions and then promoted
to floating point and integer registers. Since there are more floating
point registers than integer registers, this can cause situations where
floating point arguments are assigned to registers after integer
arguments that where assigned to the stack.

Use the inreg flag to indicate 32-bit fragments of structs containing
both float and int members.

The three-way shadowing between stack, integer, and floating point
registers requires custom argument lowering. The good news is that
return values are passed in the exact same way, and we can share the
code.

Still missing:

 - Update LowerReturn to handle structs returned in registers.
 - LowerCall.
 - Variadic functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178958 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agotypo
Nadav Rotem [Sat, 6 Apr 2013 04:24:12 +0000 (04:24 +0000)]
typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178949 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove last use of InMemoryStruct from MachOObjectFile.cpp.
Rafael Espindola [Sat, 6 Apr 2013 03:50:05 +0000 (03:50 +0000)]
Remove last use of InMemoryStruct from MachOObjectFile.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178948 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDon't use InMemoryStruct<macho::SymtabLoadCommand>.
Rafael Espindola [Sat, 6 Apr 2013 03:31:08 +0000 (03:31 +0000)]
Don't use InMemoryStruct<macho::SymtabLoadCommand>.

This also required not using the RegisterStringTable API, which is also a
good thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178947 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDon't use InMemoryStruct in getSymbol64TableEntry.
Rafael Espindola [Sat, 6 Apr 2013 02:15:44 +0000 (02:15 +0000)]
Don't use InMemoryStruct in getSymbol64TableEntry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178946 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDon't use InMemoryStruct in getSymbolTableEntry.
Rafael Espindola [Sat, 6 Apr 2013 01:59:05 +0000 (01:59 +0000)]
Don't use InMemoryStruct in getSymbolTableEntry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178945 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDon't use InMemoryStruct in getRelocation.
Rafael Espindola [Sat, 6 Apr 2013 01:24:11 +0000 (01:24 +0000)]
Don't use InMemoryStruct in getRelocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178943 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDwarf: use utostr on CUID to append to SmallString.
Manman Ren [Sat, 6 Apr 2013 01:02:38 +0000 (01:02 +0000)]
Dwarf: use utostr on CUID to append to SmallString.

We used to do "SmallString += CUID", which is incorrect, since CUID will
be truncated to a char.

rdar://problem/13573833

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178941 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemoved trailing whitespace.
Michael Gottesman [Fri, 5 Apr 2013 23:46:45 +0000 (23:46 +0000)]
Removed trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178932 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600/SI: Add support for buffer stores v2
Tom Stellard [Fri, 5 Apr 2013 23:31:51 +0000 (23:31 +0000)]
R600/SI: Add support for buffer stores v2

v2:
  - Use the ADDR64 bit

Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178931 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600/SI: Use same names for corresponding MUBUF operands and encoding fields
Tom Stellard [Fri, 5 Apr 2013 23:31:44 +0000 (23:31 +0000)]
R600/SI: Use same names for corresponding MUBUF operands and encoding fields

The code emitter knows how to encode operands whose name matches one of
the encoding fields.  If there is no match, the code emitter relies on
the order of the operand and field definitions to determine how operands
should be encoding.  Matching by order makes it easy to accidentally break
the instruction encodings, so we prefer to match by name.

Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178930 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Add RV670 processor
Tom Stellard [Fri, 5 Apr 2013 23:31:40 +0000 (23:31 +0000)]
R600: Add RV670 processor

This is an R600 GPU with double support.

Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178929 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600/SI: Add processor types for each SI variant
Tom Stellard [Fri, 5 Apr 2013 23:31:35 +0000 (23:31 +0000)]
R600/SI: Add processor types for each SI variant

Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178928 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600/SI: Avoid generating S_MOVs with 64-bit immediates v2
Tom Stellard [Fri, 5 Apr 2013 23:31:20 +0000 (23:31 +0000)]
R600/SI: Avoid generating S_MOVs with 64-bit immediates v2

SITargetLowering::analyzeImmediate() was converting the 64-bit values
to 32-bit and then checking if they were an inline immediate.  Some
of these conversions caused this check to succeed and produced
S_MOV instructions with 64-bit immediates, which are illegal.

v2:
  - Clean up logic

Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178927 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoEnable early if conversion on PPC
Hal Finkel [Fri, 5 Apr 2013 23:29:01 +0000 (23:29 +0000)]
Enable early if conversion on PPC

On cores for which we know the misprediction penalty, and we have
the isel instruction, we can profitably perform early if conversion.
This enables us to replace some small branch sequences with selects
and avoid the potential stalls from mispredicting the branches.

Enabling this feature required implementing canInsertSelect and
insertSelect in PPCInstrInfo; isel code in PPCISelLowering was
refactored to use these functions as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178926 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoCorrect the PPC A2 misprediction penalty
Hal Finkel [Fri, 5 Apr 2013 23:28:58 +0000 (23:28 +0000)]
Correct the PPC A2 misprediction penalty

The manual states that there is a minimum of 13 cycles from when the
mispredicted branch is issued to when the correct branch target is
issued.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178925 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAn objc_retain can serve as a use for a different pointer.
Michael Gottesman [Fri, 5 Apr 2013 22:54:32 +0000 (22:54 +0000)]
An objc_retain can serve as a use for a different pointer.

This is the counterpart to commit r160637, except it performs the action
in the bottomup portion of the data flow analysis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178922 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoProperly model precise lifetime when given an incomplete dataflow sequence.
Michael Gottesman [Fri, 5 Apr 2013 22:54:28 +0000 (22:54 +0000)]
Properly model precise lifetime when given an incomplete dataflow sequence.

The normal dataflow sequence in the ARC optimizer consists of the following
states:

    Retain -> CanRelease -> Use -> Release

The optimizer before this patch stored the uses that determine the lifetime of
the retainable object pointer when it bottom up hits a retain or when top down
it hits a release. This is correct for an imprecise lifetime scenario since what
we are trying to do is remove retains/releases while making sure that no
``CanRelease'' (which is usually a call) deallocates the given pointer before we
get to the ``Use'' (since that would cause a segfault).

If we are considering the precise lifetime scenario though, this is not
correct. In such a situation, we *DO* care about the previous sequence, but
additionally, we wish to track the uses resulting from the following incomplete
sequences:

  Retain -> CanRelease -> Release   (TopDown)
  Retain <- Use <- Release          (BottomUp)

*NOTE* This patch looks large but the most of it consists of updating
test cases. Additionally this fix exposed an additional bug. I removed
the test case that expressed said bug and will recommit it with the fix
in a little bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178921 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoReapply r178845 with fix - Fix bug in PEI's virtual-register scavenging
Hal Finkel [Fri, 5 Apr 2013 22:31:56 +0000 (22:31 +0000)]
Reapply r178845 with fix - Fix bug in PEI's virtual-register scavenging

This fixes PEI as previously described, but correctly handles the case where
the instruction defining the virtual register to be scavenged is the first in
the block. Arnold provided me with a bugpoint-reduced test case, but even that
seems too large to use as a regression test. If I'm successful in cleaning it
up then I'll commit that as well.

Original commit message:

    This change fixes a bug that I introduced in r178058. After a register is
    scavenged using one of the available spills slots the instruction defining the
    virtual register needs to be moved to after the spill code. The scavenger has
    already processed the defining instruction so that registers killed by that
    instruction are available for definition in that same instruction. Unfortunately,
    after this, the scavenger needs to iterate through the spill code and then
    visit, again, the instruction that defines the now-scavenged register. In order
    to avoid confusion, the register scavenger needs the ability to 'back up'
    through the spill code so that it can again process the instructions in the
    appropriate order. Prior to this fix, once the scavenger reached the
    just-moved instruction, it would assert if it killed any registers because,
    having already processed the instruction, it believed they were undefined.

    Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar
    for diagnosing the problem and testing this fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178919 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse the target options specified on a function to reset the back-end.
Bill Wendling [Fri, 5 Apr 2013 21:52:40 +0000 (21:52 +0000)]
Use the target options specified on a function to reset the back-end.

During LTO, the target options on functions within the same Module may
change. This would necessitate resetting some of the back-end. Do this for X86,
because it's a Friday afternoon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178917 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRevert r178845 - Fix bug in PEI's virtual-register scavenging
Hal Finkel [Fri, 5 Apr 2013 21:30:40 +0000 (21:30 +0000)]
Revert r178845 - Fix bug in PEI's virtual-register scavenging

Reverting because this breaks one of the LTO builders. Original commit message:

    This change fixes a bug that I introduced in r178058. After a register is
    scavenged using one of the available spills slots the instruction defining the
    virtual register needs to be moved to after the spill code. The scavenger has
    already processed the defining instruction so that registers killed by that
    instruction are available for definition in that same instruction. Unfortunately,
    after this, the scavenger needs to iterate through the spill code and then
    visit, again, the instruction that defines the now-scavenged register. In order
    to avoid confusion, the register scavenger needs the ability to 'back up'
    through the spill code so that it can again process the instructions in the
    appropriate order. Prior to this fix, once the scavenger reached the
    just-moved instruction, it would assert if it killed any registers because,
    having already processed the instruction, it believed they were undefined.

    Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar
    for diagnosing the problem and testing this fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178916 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoTidy up a bit. No functional change.
Jim Grosbach [Fri, 5 Apr 2013 21:20:12 +0000 (21:20 +0000)]
Tidy up a bit. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178915 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDisable the optimization about promoting vector-element-access with symbolic index.
Shuxin Yang [Fri, 5 Apr 2013 21:07:08 +0000 (21:07 +0000)]
Disable the optimization about promoting vector-element-access with symbolic index.

This optimization is unstable at this moment; it
  1) block us on a very important application
  2) PR15200
  3) test6 and test7 in test/Transforms/ScalarRepl/dynamic-vector-gep.ll
     (the CHECK command compare the output against wrong result)

   I personally believe this optimization should not have any impact on the
autovectorized code, as auto-vectorizer is supposed to put gather/scatter
in a "right" way.  Although in theory downstream optimizaters might reveal
some gather/scatter optimization opportunities, the chance is quite slim.

   For the hand-crafted vectorizing code, in term of redundancy elimination,
load-CSE, copy-propagation and DSE can collectively achieve the same result,
but in much simpler way. On the other hand, these optimizers are able to
improve the code in a incremental way; in contrast, SROA is sort of all-or-none
approach. However, SROA might slighly win in stack size, as it tries to figure
out a stretch of memory tightenly cover the area accessed by the dynamic index.

 rdar://13174884
 PR15200

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178912 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] XFAIL test-interp-vec-loadstore.ll in an attempt to turn builder
Akira Hatanaka [Fri, 5 Apr 2013 20:54:46 +0000 (20:54 +0000)]
[mips] XFAIL test-interp-vec-loadstore.ll in an attempt to turn builder
llvm-mips-linux green.

llvm-mips-linux runs on a big endian machine. This test passes if I change 'e'
to 'E' in the target data layout string.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178910 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago<rdar://problem/13551789> Fix a race in the LockFileManager.
Douglas Gregor [Fri, 5 Apr 2013 20:53:57 +0000 (20:53 +0000)]
<rdar://problem/13551789> Fix a race in the LockFileManager.

It's possible for the lock file to disappear and the owning process to
return before we're able to see the generated file. Spin for a little
while to see if it shows up before failing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178909 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago<rdar://problem/13551789> Fix yet another race in unique_file.
Douglas Gregor [Fri, 5 Apr 2013 20:48:36 +0000 (20:48 +0000)]
<rdar://problem/13551789> Fix yet another race in unique_file.

If the directory that will contain the unique file doesn't exist when
we tried to create the file, but another process creates it before we
get a chance to try creating it, we would bail out rather than try to
create the unique file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178908 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[Support][FileSystem] Fix identify_magic for big endian ELF.
Michael J. Spencer [Fri, 5 Apr 2013 20:10:04 +0000 (20:10 +0000)]
[Support][FileSystem] Fix identify_magic for big endian ELF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178905 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMove yaml2obj to tools too.
Rafael Espindola [Fri, 5 Apr 2013 20:00:35 +0000 (20:00 +0000)]
Move yaml2obj to tools too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178904 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDefine versions of Section that are explicitly marked as little endian.
Rafael Espindola [Fri, 5 Apr 2013 18:45:28 +0000 (18:45 +0000)]
Define versions of Section that are explicitly marked as little endian.

These should really be templated like ELF, but this is a start.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178896 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdded two debug logging messages to VisitInstructionsTopDown to match VisitInstructio...
Michael Gottesman [Fri, 5 Apr 2013 18:26:08 +0000 (18:26 +0000)]
Added two debug logging messages to VisitInstructionsTopDown to match VisitInstructionsBottomUp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178895 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDon't use InMemoryStruct in getSection and getSection64.
Rafael Espindola [Fri, 5 Apr 2013 18:18:19 +0000 (18:18 +0000)]
Don't use InMemoryStruct in getSection and getSection64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178894 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoCleaned up whitespace and made debug logging less verbose.
Michael Gottesman [Fri, 5 Apr 2013 18:10:41 +0000 (18:10 +0000)]
Cleaned up whitespace and made debug logging less verbose.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178893 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMake the test/CodeGen/X86/win32_sret.ll reliable on any CPU by explicitly specifying...
Timur Iskhodzhanov [Fri, 5 Apr 2013 17:05:56 +0000 (17:05 +0000)]
Make the test/CodeGen/X86/win32_sret.ll reliable on any CPU by explicitly specifying the -mcpu

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178885 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoReverting 178851 as it broke buildbots
Renato Golin [Fri, 5 Apr 2013 16:39:53 +0000 (16:39 +0000)]
Reverting 178851 as it broke buildbots

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178883 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[ms-inline asm] Add support for numeric displacement expressions in bracketed
Chad Rosier [Fri, 5 Apr 2013 16:28:55 +0000 (16:28 +0000)]
[ms-inline asm] Add support for numeric displacement expressions in bracketed
memory operands.

Essentially, this layers an infix calculator on top of the parsing state
machine.  The scale on the index register is still expected to be an immediate

 __asm mov eax, [eax + ebx*4]

and will not work with more complex expressions.  For example,

 __asm mov eax, [eax + ebx*(2*2)]

The plus and minus binary operators assume the numeric value of a register is
zero so as to not change the displacement.  Register operands should never
be an operand for a multiply or divide operation; the scale*indexreg
expression is always replaced with a zero on the operand stack to prevent
such a case.
rdar://13521380

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178881 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[Support] Disable assertion dialogs from the MSVC debug CRT
Reid Kleckner [Fri, 5 Apr 2013 16:18:03 +0000 (16:18 +0000)]
[Support] Disable assertion dialogs from the MSVC debug CRT

Summary:
Sets a report hook that emulates pressing "retry" in the "abort, retry,
ignore" dialog box that _CrtDbgReport normally raises.  There are many
other ways to disable assertion reports, but this was the only way I
could find that still calls our exception handler.

Reviewers: Bigcheese

CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D625

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178880 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse ScalarBitSetTraits.
Rafael Espindola [Fri, 5 Apr 2013 16:00:31 +0000 (16:00 +0000)]
Use ScalarBitSetTraits.

What was missing was were the type strong operator|.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178879 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix include guards to match new location.
Rafael Espindola [Fri, 5 Apr 2013 15:31:16 +0000 (15:31 +0000)]
Fix include guards to match new location.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178877 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDon't fetch pointers from a InMemoryStruct.
Rafael Espindola [Fri, 5 Apr 2013 15:15:22 +0000 (15:15 +0000)]
Don't fetch pointers from a InMemoryStruct.

InMemoryStruct is extremely dangerous as it returns data from an internal
buffer when the endiannes doesn't match. This should fix the tests on big
endian hosts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178875 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoEnable JIT/MCJIT unit tests for targets with JIT support.
Jyotsna Verma [Fri, 5 Apr 2013 14:26:16 +0000 (14:26 +0000)]
Enable JIT/MCJIT unit tests for targets with JIT support.
Change unittests/ExecutionEngine/Makefile to include Makefile.config before
TARGET_HAS_JIT flag is checked.

Fixes bug: http://llvm.org/bugs/show_bug.cgi?id=15669

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178871 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRespect Addend when processing MCJIT relocations to local/global symbols.
Ulrich Weigand [Fri, 5 Apr 2013 13:29:04 +0000 (13:29 +0000)]
Respect Addend when processing MCJIT relocations to local/global symbols.

When the RuntimeDyldELF::processRelocationRef routine finds the target
symbol of a relocation in the local or global symbol table, it performs
a section-relative relocation:

    Value.SectionID = lsi->second.first;
    Value.Addend = lsi->second.second;

At this point, however, any Addend that might have been specified in
the original relocation record is lost.  This is somewhat difficult to
trigger for relocations within the code section since they usually
do not contain non-zero Addends (when built with the default JIT code
model, in any case).  However, the problem can be reliably triggered
by a relocation within the data section caused by code like:

 int test[2] = { -1, 0 };
 int *p = &test[1];

The initializer of "p" will need a relocation to "test + 4".  On
platforms using RelA relocations this means an Addend of 4 is required.
Current code ignores this addend when processing the relocation,
resulting in incorrect execution.

Fixed by taking the Addend into account when processing relocations
to symbols found in the local or global symbol table.

Tested on x86_64-linux and powerpc64-linux.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178869 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agollvm-symbolizer: correctly parse filenames given in quotes
Alexey Samsonov [Fri, 5 Apr 2013 09:22:24 +0000 (09:22 +0000)]
llvm-symbolizer: correctly parse filenames given in quotes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178859 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd a basic test for llvm-symbolizer tool
Alexey Samsonov [Fri, 5 Apr 2013 08:30:13 +0000 (08:30 +0000)]
Add a basic test for llvm-symbolizer tool

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178858 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoBuildbot fix for r178851: mistake was in wrong TargetRegisterInfo::getRegClass usage.
Stepan Dyatkovskiy [Fri, 5 Apr 2013 07:34:08 +0000 (07:34 +0000)]
Buildbot fix for r178851: mistake was in wrong TargetRegisterInfo::getRegClass usage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178854 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd obj2yaml to test dependencies
Alexey Samsonov [Fri, 5 Apr 2013 07:26:37 +0000 (07:26 +0000)]
Add obj2yaml to test dependencies

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178852 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix for PR14824: "Optimization arm_ldst_opt inserts newly generated instruction vldmi...
Stepan Dyatkovskiy [Fri, 5 Apr 2013 05:52:14 +0000 (05:52 +0000)]
Fix for PR14824: "Optimization arm_ldst_opt inserts newly generated instruction vldmia at incorrect position".
Patch introduces memory operands tracking in ARMLoadStoreOpt::LoadStoreMultipleOpti. For each register it keeps the order of load operations as it was before optimization pass.
It is kind of deep improvement of fix proposed by Hao: http://llvm.org/bugs/show_bug.cgi?id=14824#c4
But it also tracks conflicts between different register classes (e.g. D2 and S5).
For more details see:
Bug description: http://llvm.org/bugs/show_bug.cgi?id=14824
LLVM Commits discussion:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130311/167936.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130318/168688.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130325/169376.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130401/170238.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178851 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd a SchedMachineModel for the PPC G5
Hal Finkel [Fri, 5 Apr 2013 05:49:18 +0000 (05:49 +0000)]
Add a SchedMachineModel for the PPC G5

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178850 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoThe ppc bots say this is the last broken line, so lets try one more :-(
Rafael Espindola [Fri, 5 Apr 2013 05:36:37 +0000 (05:36 +0000)]
The ppc bots say this is the last broken line, so lets try one more :-(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178849 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd a SchedMachineModel for the PPC A2
Hal Finkel [Fri, 5 Apr 2013 05:34:08 +0000 (05:34 +0000)]
Add a SchedMachineModel for the PPC A2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178848 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoOne more try before I just delete the macho bits until tomorrow.
Rafael Espindola [Fri, 5 Apr 2013 05:15:39 +0000 (05:15 +0000)]
One more try before I just delete the macho bits until tomorrow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178847 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix bug in PEI's virtual-register scavenging
Hal Finkel [Fri, 5 Apr 2013 05:01:13 +0000 (05:01 +0000)]
Fix bug in PEI's virtual-register scavenging

This change fixes a bug that I introduced in r178058. After a register is
scavenged using one of the available spills slots the instruction defining the
virtual register needs to be moved to after the spill code. The scavenger has
already processed the defining instruction so that registers killed by that
instruction are available for definition in that same instruction. Unfortunately,
after this, the scavenger needs to iterate through the spill code and then
visit, again, the instruction that defines the now-scavenged register. In order
to avoid confusion, the register scavenger needs the ability to 'back up'
through the spill code so that it can again process the instructions in the
appropriate order. Prior to this fix, once the scavenger reached the
just-moved instruction, it would assert if it killed any registers because,
having already processed the instruction, it believed they were undefined.

Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar
for diagnosing the problem and testing this fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178845 91177308-0d34-0410-b5e6-96231b3b80d8