Implement promotion for EXTRACT_VECTOR_ELT, allowing v16i8 multiplies to work with PowerPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27349 91177308-0d34-0410-b5e6-96231b3b80d8

add a note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27348 91177308-0d34-0410-b5e6-96231b3b80d8

Implement the Expand action for binary vector operations to break the binop
into elements and operate on each piece.  This allows generic vector integer
multiplies to work on PPC, though the generated code is horrible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27347 91177308-0d34-0410-b5e6-96231b3b80d8

Intrinsics that just load from memory can be treated like loads: they don't
have to serialize against each other.  This allows us to schedule lvx's
across each other, for example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27346 91177308-0d34-0410-b5e6-96231b3b80d8

Adjust the Intrinsics.gen interface a little bit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27345 91177308-0d34-0410-b5e6-96231b3b80d8

Adjust to change in Intrinsics.gen interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27344 91177308-0d34-0410-b5e6-96231b3b80d8

Constant fold all of the vector binops.  This allows us to compile this:

"vector unsigned char mergeLowHigh = (vector unsigned char)
( 8, 9, 10, 11, 16, 17, 18, 19, 12, 13, 14, 15, 20, 21, 22, 23 );
vector unsigned char mergeHighLow = vec_xor( mergeLowHigh, vec_splat_u8(8));"

aka:

void %test2(<16 x sbyte>* %P) {
  store <16 x sbyte> cast (<4 x int> xor (<4 x int> cast (<16 x ubyte> < ubyte 8, ubyte 9, ubyte 10, ubyte 11, ubyte 16, ubyte 17, ubyte 18, ubyte 19, ubyte 12, ubyte 13, ubyte 14, ubyte 15, ubyte 20, ubyte 21, ubyte 22, ubyte 23 > to <4 x int>), <4 x int> cast (<16 x sbyte> < sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8 > to <4 x int>)) to <16 x sbyte>), <16 x sbyte> * %P
  ret void
}

into this:

_test2:
        mfspr r2, 256
        oris r4, r2, 32768
        mtspr 256, r4
        li r4, lo16(LCPI2_0)
        lis r5, ha16(LCPI2_0)
        lvx v0, r5, r4
        stvx v0, 0, r3
        mtspr 256, r2
        blr

instead of this:

_test2:
        mfspr r2, 256
        oris r4, r2, 49152
        mtspr 256, r4
        li r4, lo16(LCPI2_0)
        lis r5, ha16(LCPI2_0)
        vspltisb v0, 8
        lvx v1, r5, r4
        vxor v0, v1, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

... which occurs here:
http://developer.apple.com/hardware/ve/calcspeed.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27343 91177308-0d34-0410-b5e6-96231b3b80d8

Add a new -view-legalize-dags command line option

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27342 91177308-0d34-0410-b5e6-96231b3b80d8

Implement constant folding of bit_convert of arbitrary constant vbuild_vector nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27341 91177308-0d34-0410-b5e6-96231b3b80d8

These entries already exist

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27340 91177308-0d34-0410-b5e6-96231b3b80d8

Add some missing node names

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27339 91177308-0d34-0410-b5e6-96231b3b80d8

simplify this method

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27338 91177308-0d34-0410-b5e6-96231b3b80d8

New note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27337 91177308-0d34-0410-b5e6-96231b3b80d8

Constant fold casts from things like <4 x int> -> <4 x uint>, likewise int<->fp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27336 91177308-0d34-0410-b5e6-96231b3b80d8

Custom lower all BUILD_VECTOR's so that we can compile vec_splat_u8(8) into
"vspltisb v0, 8" instead of a constant pool load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27335 91177308-0d34-0410-b5e6-96231b3b80d8

Prefer larger register classes over smaller ones when a register occurs in
multiple register classes.  This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27334 91177308-0d34-0410-b5e6-96231b3b80d8

New testcase that crashes the compiler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27333 91177308-0d34-0410-b5e6-96231b3b80d8

add valuemapper support for inline asm

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27332 91177308-0d34-0410-b5e6-96231b3b80d8

Implement vnot using VNOR instead of using 'vspltisb v0, -1' and vxor

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27331 91177308-0d34-0410-b5e6-96231b3b80d8

Fix InstCombine/2006-04-01-InfLoop.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27330 91177308-0d34-0410-b5e6-96231b3b80d8

New testcase that caused instcombine to infinitely loop (with my recent
patch), distilled from Applications/JM/ldecod

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27329 91177308-0d34-0410-b5e6-96231b3b80d8

Fold A^(B&A) -> (B&A)^A
Fold (B&A)^A == ~B & A

This implements InstCombine/xor.ll:test2[56]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27328 91177308-0d34-0410-b5e6-96231b3b80d8

new testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27327 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll and
PR726 by performing consistent signed division, not consistent unsigned
division when evaluating scev's.  Do not touch udivs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27326 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase for PR726

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27325 91177308-0d34-0410-b5e6-96231b3b80d8

ADd a note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27324 91177308-0d34-0410-b5e6-96231b3b80d8

If we can look through vector operations to find the scalar version of an
extract_element'd value, do so.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27323 91177308-0d34-0410-b5e6-96231b3b80d8

Shrinkify some more intrinsic definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27322 91177308-0d34-0410-b5e6-96231b3b80d8

An entry about packed type alignments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27321 91177308-0d34-0410-b5e6-96231b3b80d8

Pull operand asm string into base class, shrinkifying intrinsic definitions.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27320 91177308-0d34-0410-b5e6-96231b3b80d8

TargetData.cpp::getTypeInfo() was returning alignment of element type as the
alignment of a packed type. This is obviously wrong. Added a workaround that
returns the size of the packed type as its alignment. The correct fix would
be to return a target dependent alignment value provided via TargetLowering
(or some other interface).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27319 91177308-0d34-0410-b5e6-96231b3b80d8

Delete identity shuffles, implementing CodeGen/Generic/vector-identity-shuffle.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27317 91177308-0d34-0410-b5e6-96231b3b80d8

An identity shuffle shouldn't generate any permute code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27316 91177308-0d34-0410-b5e6-96231b3b80d8

Fix 80 column violations :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27315 91177308-0d34-0410-b5e6-96231b3b80d8

Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed
INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27314 91177308-0d34-0410-b5e6-96231b3b80d8

regenerate

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27313 91177308-0d34-0410-b5e6-96231b3b80d8

Generalize the previous binary operator support and add a string concatenation
operation.  This implements Regression/TableGen/strconcat.td.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27312 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27311 91177308-0d34-0410-b5e6-96231b3b80d8

Added support for SSE3 horizontal ops: haddp{s|d} and hsub{s|d}.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27310 91177308-0d34-0410-b5e6-96231b3b80d8

Added haddp{s|d} and hsubp{s|d} intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27309 91177308-0d34-0410-b5e6-96231b3b80d8

fix a pasto

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27308 91177308-0d34-0410-b5e6-96231b3b80d8

Add vperm support for all datatypes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27307 91177308-0d34-0410-b5e6-96231b3b80d8

Rearrange code a bit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27306 91177308-0d34-0410-b5e6-96231b3b80d8

Add, sub and shuffle are legal for all vector types

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27305 91177308-0d34-0410-b5e6-96231b3b80d8

Add support to use pextrw and pinsrw to extract and insert a word element
from a 128-bit vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27304 91177308-0d34-0410-b5e6-96231b3b80d8

Add vector_extract and vector_insert nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27303 91177308-0d34-0410-b5e6-96231b3b80d8

add a note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27302 91177308-0d34-0410-b5e6-96231b3b80d8

constant fold extractelement with undef operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27301 91177308-0d34-0410-b5e6-96231b3b80d8

extractelement(undef,x) -> undef

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27300 91177308-0d34-0410-b5e6-96231b3b80d8

Do not endian swap split vector loads.  This fixes UnitTests/Vector/sumarray-dbl on PPC.

Now all UnitTests/Vector/* tests pass on PPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27299 91177308-0d34-0410-b5e6-96231b3b80d8

Do not endian swap the operands to a store if the operands came from a vector.

This fixes UnitTests/Vector/simple.c with altivec.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27298 91177308-0d34-0410-b5e6-96231b3b80d8

Remove dead *extloads.  This allows us to codegen vector.ll:test_extract_elt
to:

test_extract_elt:
        alloc r3 = ar.pfs,0,1,0,0
        adds r8 = 12, r32
        ;;
        ldfs f8 = [r8]
        mov ar.pfs = r3
        br.ret.sptk.many rp

instead of:

test_extract_elt:
        alloc r3 = ar.pfs,0,1,0,0
        adds r8 = 28, r32
        adds r9 = 24, r32
        adds r10 = 20, r32
        adds r11 = 16, r32
        ;;
        ldfs f6 = [r8]
        ;;
        ldfs f6 = [r9]
        adds r8 = 12, r32
        adds r9 = 8, r32
        adds r14 = 4, r32
        ;;
        ldfs f6 = [r10]
        ;;
        ldfs f6 = [r11]
        ldfs f8 = [r8]
        ;;
        ldfs f6 = [r9]
        ;;
        ldfs f6 = [r14]
        ;;
        ldfs f6 = [r32]
        mov ar.pfs = r3
        br.ret.sptk.many rp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27297 91177308-0d34-0410-b5e6-96231b3b80d8

Delete dead loads in the dag.  This allows us to compile
vector.ll:test_extract_elt2 into:

_test_extract_elt2:
        lfd f1, 32(r3)
        blr

instead of:

_test_extract_elt2:
        lfd f0, 56(r3)
        lfd f0, 48(r3)
        lfd f0, 40(r3)
        lfd f1, 32(r3)
        lfd f0, 24(r3)
        lfd f0, 16(r3)
        lfd f0, 8(r3)
        lfd f0, 0(r3)
        blr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27296 91177308-0d34-0410-b5e6-96231b3b80d8

Make this test harder, always check generic x86 and SSE-enabled x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27295 91177308-0d34-0410-b5e6-96231b3b80d8

Implement PromoteOp for VEXTRACT_VECTOR_ELT.  Thsi fixes
Generic/vector.ll:test_extract_elt on non-sse X86 systems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27294 91177308-0d34-0410-b5e6-96231b3b80d8

Scalarized vector stores need not be legal, e.g. if the vector element type
needs to be promoted or expanded.  Relegalize the scalar store once created.
This fixes CodeGen/Generic/vector.ll:test1 on non-SSE x86 targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27293 91177308-0d34-0410-b5e6-96231b3b80d8

Fix build breakage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27292 91177308-0d34-0410-b5e6-96231b3b80d8

note to self: *save* file, then check it in

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27291 91177308-0d34-0410-b5e6-96231b3b80d8

Implement an item from the readme, folding vcmp/vcmp. instructions with
identical instructions into a single instruction.  For example, for:

void test(vector float *x, vector float *y, int *P) {
  int v = vec_any_out(*x, *y);
  *x = (vector float)vec_cmpb(*x, *y);
  *P = v;
}

we now generate:

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v0, v1, v0
        mfcr r4, 2
        stvx v0, 0, r3
        rlwinm r3, r4, 27, 31, 31
        xori r3, r3, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

instead of:

_test:
        mfspr r2, 256
        oris r6, r2, 57344
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v2, v1, v0
        mfcr r4, 2
***     vcmpbfp v0, v1, v0
        rlwinm r4, r4, 27, 31, 31
        stvx v0, 0, r3
        xori r3, r4, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

Testcase here: CodeGen/PowerPC/vcmp-fold.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27290 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27289 91177308-0d34-0410-b5e6-96231b3b80d8

compactify some more instruction definitions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27288 91177308-0d34-0410-b5e6-96231b3b80d8

Compactify comparisons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27287 91177308-0d34-0410-b5e6-96231b3b80d8

Allow bits init values to be used in patterns, turn them into ints.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27286 91177308-0d34-0410-b5e6-96231b3b80d8

Lower vector compares to VCMP nodes, just like we lower vector comparison
predicates to VCMPo nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27285 91177308-0d34-0410-b5e6-96231b3b80d8

These are done

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27284 91177308-0d34-0410-b5e6-96231b3b80d8

Final bugfix for PR724.  GCC won't inline varargs functions, so use one to
validate the prototype of intrinsic functions.  This prevents GCC from going
crazy and inlining too much stuff, eventually running out of memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27283 91177308-0d34-0410-b5e6-96231b3b80d8

Add a new method to verify intrinsic function prototypes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27282 91177308-0d34-0410-b5e6-96231b3b80d8

When emitting code for the verifier, instead of emitting each case statement
independently, batch up checks so that identically typed intrinsics share
verifier code.  This dramatically reduces the size of the verifier function,
which should help avoid GCC running out of memory compiling Verifier.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27281 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure to pass enough values to phi nodes when we are dealing with
decimated vectors.  This fixes UnitTests/Vector/sumarray-dbl.c

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27280 91177308-0d34-0410-b5e6-96231b3b80d8

Significantly improve handling of vectors that are live across basic blocks,
handling cases where the vector elements need promotion, expansion, and when
the vector type itself needs to be decimated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27278 91177308-0d34-0410-b5e6-96231b3b80d8

Was returning the wrong type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27277 91177308-0d34-0410-b5e6-96231b3b80d8

Mark INSERT_VECTOR_ELT as expand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27276 91177308-0d34-0410-b5e6-96231b3b80d8

Expand all INSERT_VECTOR_ELT (obviously bad) for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27275 91177308-0d34-0410-b5e6-96231b3b80d8

Expand INSERT_VECTOR_ELT to store vec, sp; store elt, sp+k; vec = load sp;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27274 91177308-0d34-0410-b5e6-96231b3b80d8

Modify the TargetLowering::getPackedTypeBreakdown method to also return the
unpromoted element type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27273 91177308-0d34-0410-b5e6-96231b3b80d8

Typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27272 91177308-0d34-0410-b5e6-96231b3b80d8

Ok for vector_shuffle mask to contain undef elements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27271 91177308-0d34-0410-b5e6-96231b3b80d8

Implement TargetLowering::getPackedTypeBreakdown

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27270 91177308-0d34-0410-b5e6-96231b3b80d8

Add a method useful for decimating vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27269 91177308-0d34-0410-b5e6-96231b3b80d8

Add the rest of the vmul instructions and the vmulsum* instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27268 91177308-0d34-0410-b5e6-96231b3b80d8

fix incorrect prototypes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27267 91177308-0d34-0410-b5e6-96231b3b80d8

Use a new tblgen feature to significantly shrinkify instruction definitions that
directly correspond to intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27266 91177308-0d34-0410-b5e6-96231b3b80d8

Add a bunch of new instructions for intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27265 91177308-0d34-0410-b5e6-96231b3b80d8

regenerate

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27264 91177308-0d34-0410-b5e6-96231b3b80d8

Implement Regression/TableGen/DagDefSubst.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27263 91177308-0d34-0410-b5e6-96231b3b80d8

Dag operator should be able to be template params.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27262 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Transforms/InstCombine/2006-03-30-ExtractElement.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27261 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase that crashes instcombine

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27260 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure all possible shuffles are matched.
Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27259 91177308-0d34-0410-b5e6-96231b3b80d8

Add vector multiply, multiply sum, pack, unpack, and lvsl/lvsr intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27258 91177308-0d34-0410-b5e6-96231b3b80d8

More logical ops patterns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27257 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27256 91177308-0d34-0410-b5e6-96231b3b80d8

Add 128-bit pmovmskb intrinsic support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27255 91177308-0d34-0410-b5e6-96231b3b80d8

Change SSE pack operation definitions to fit what the intrinsics expected.
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27254 91177308-0d34-0410-b5e6-96231b3b80d8

Add SSE2 integer pack with saturation intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27253 91177308-0d34-0410-b5e6-96231b3b80d8

- Added some SSE2 128-bit packed integer ops.
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27252 91177308-0d34-0410-b5e6-96231b3b80d8

Add a pshufhw test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27251 91177308-0d34-0410-b5e6-96231b3b80d8

Need to special case splat after all. Make the second operand of splat
vector_shuffle undef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27250 91177308-0d34-0410-b5e6-96231b3b80d8

Use unpcklpd for v2f64 splat.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27249 91177308-0d34-0410-b5e6-96231b3b80d8

Floating point logical operation patterns should match bit_convert. Or else
integer vector logical operations would match andp{s|d} instead of pand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27248 91177308-0d34-0410-b5e6-96231b3b80d8