oota-llvm.git
10 years agoRemove a method that was just replacing direct access to a member.
Eric Christopher [Tue, 10 Jun 2014 22:57:21 +0000 (22:57 +0000)]
Remove a method that was just replacing direct access to a member.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210598 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agolit: warn when passed invalid pathname
Hans Wennborg [Tue, 10 Jun 2014 22:51:58 +0000 (22:51 +0000)]
lit: warn when passed invalid pathname

It would previously say things like

  warning: input 'test/Frontend/foo.c' contained no tests

and have the user pull their hair trying to figure out what's wrong with that
file. This patch changes the message to the much clearer:

  warning: no such file or directory: 'test/Frontend/foo.c'

Differential Revision: http://reviews.llvm.org/D4097

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210597 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove the use of TargetMachine from X86InstrInfo.
Eric Christopher [Tue, 10 Jun 2014 22:34:31 +0000 (22:34 +0000)]
Remove the use of TargetMachine from X86InstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210596 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMove X86RegisterInfo away from using the TargetMachine and only
Eric Christopher [Tue, 10 Jun 2014 22:34:28 +0000 (22:34 +0000)]
Move X86RegisterInfo away from using the TargetMachine and only
using the subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210595 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMark a few functions noexcept.
Rafael Espindola [Tue, 10 Jun 2014 21:26:47 +0000 (21:26 +0000)]
Mark a few functions noexcept.

This reduces the difference between std::error_code and llvm::error_code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210591 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoUse the TargetMachine on the DAG or the MachineFunction instead
Eric Christopher [Tue, 10 Jun 2014 21:25:13 +0000 (21:25 +0000)]
Use the TargetMachine on the DAG or the MachineFunction instead
of using the cached TargetMachine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210589 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600/SI: Emit an error when attempting to spill VGPRs v4
Tom Stellard [Tue, 10 Jun 2014 21:20:41 +0000 (21:20 +0000)]
R600/SI: Emit an error when attempting to spill VGPRs v4

I can't get VGPR spilling to work reliable, so for now just emit
an error when the register allocator tries to spill VGPRs.

v2:
  - Fix build
v3:
  - Added crash fix when spilling SPGRs
v4:
  - Use V_MOV_B32 as a dummy instruction instead of S_NOP

Patch by: Darren Powell

https://bugs.freedesktop.org/show_bug.cgi?id=75276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210588 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600/SI: Fix a crash when spilling SGPRs
Tom Stellard [Tue, 10 Jun 2014 21:20:38 +0000 (21:20 +0000)]
R600/SI: Fix a crash when spilling SGPRs

We need to make sure only one new instruction is added when spilling
otherwise the register allocator may crash.

This fixes a crash in the game Antichamber.

https://bugs.freedesktop.org/show_bug.cgi?id=75276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210587 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdd a LLVM_NOEXCEPT to Compiler.h.
Rafael Espindola [Tue, 10 Jun 2014 20:45:52 +0000 (20:45 +0000)]
Add a LLVM_NOEXCEPT to Compiler.h.

This will be needed for the switch to std::error_code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210581 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoWe already have a reference to the TargetMachine, use that.
Eric Christopher [Tue, 10 Jun 2014 20:39:39 +0000 (20:39 +0000)]
We already have a reference to the TargetMachine, use that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210580 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoHave isInTailCallPosition take the DAG so that we can use the
Eric Christopher [Tue, 10 Jun 2014 20:39:38 +0000 (20:39 +0000)]
Have isInTailCallPosition take the DAG so that we can use the
version of TargetLowering/Machine from there on the way to avoiding
TargetMachine in TargetLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210579 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoReorder includes to be sorted.
Eric Christopher [Tue, 10 Jun 2014 20:39:35 +0000 (20:39 +0000)]
Reorder includes to be sorted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210578 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRearrange the CHECK lines in this test to make failure more obvious.
Reid Kleckner [Tue, 10 Jun 2014 20:16:47 +0000 (20:16 +0000)]
Rearrange the CHECK lines in this test to make failure more obvious.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210575 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert "Patch by Ray Donnelly to print register names instead of numbers."
Reid Kleckner [Tue, 10 Jun 2014 20:16:36 +0000 (20:16 +0000)]
Revert "Patch by Ray Donnelly to print register names instead of numbers."

This reverts commit r206683.

The code was confusing SEH register numbers with DWARF register numbers.
The test case it was committed with was obviously incorrect.  The
disassembler was roundtripping '.seh_pushreg %rsi' as '.seh_pushreg
%rbp', and other exciting things.

Noticed by Vadim Chugunov.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210574 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix error in tablegen when either operand of !if is an empty list.
Matt Arsenault [Tue, 10 Jun 2014 20:10:08 +0000 (20:10 +0000)]
Fix error in tablegen when either operand of !if is an empty list.

!if([Something], []) would error with "No type for list".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210572 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix typos.
Eric Christopher [Tue, 10 Jun 2014 20:07:29 +0000 (20:07 +0000)]
Fix typos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210571 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600: Use BCNT_INT for evergreen
Matt Arsenault [Tue, 10 Jun 2014 19:18:28 +0000 (19:18 +0000)]
R600: Use BCNT_INT for evergreen

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210569 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600/SI: Implement i64 ctpop
Matt Arsenault [Tue, 10 Jun 2014 19:18:24 +0000 (19:18 +0000)]
R600/SI: Implement i64 ctpop

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210568 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600/SI: Use bcnt instruction for ctpop
Matt Arsenault [Tue, 10 Jun 2014 19:18:21 +0000 (19:18 +0000)]
R600/SI: Use bcnt instruction for ctpop

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210567 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoUse an enum class now that they are available.
Rafael Espindola [Tue, 10 Jun 2014 19:08:21 +0000 (19:08 +0000)]
Use an enum class now that they are available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210566 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600: Handle fcopysign
Matt Arsenault [Tue, 10 Jun 2014 19:00:20 +0000 (19:00 +0000)]
R600: Handle fcopysign

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210564 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600/SI: Handle sign_extend and zero_extend to i64 with patterns.
Matt Arsenault [Tue, 10 Jun 2014 18:54:59 +0000 (18:54 +0000)]
R600/SI: Handle sign_extend and zero_extend to i64 with patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210563 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdd a FIXME.
Eric Christopher [Tue, 10 Jun 2014 18:31:18 +0000 (18:31 +0000)]
Add a FIXME.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210559 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMove AArch64SelectionDAGInfo down to the subtarget.
Eric Christopher [Tue, 10 Jun 2014 18:21:53 +0000 (18:21 +0000)]
Move AArch64SelectionDAGInfo down to the subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210557 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[FastISel] Collect statistics about failing intrinsic calls.
Juergen Ributzka [Tue, 10 Jun 2014 18:17:00 +0000 (18:17 +0000)]
[FastISel] Collect statistics about failing intrinsic calls.

Add more instruction-specific statistics about failing intrinsic calls during
FastISel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210556 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove the cached little endian variable. We can get it easily off
Eric Christopher [Tue, 10 Jun 2014 18:11:20 +0000 (18:11 +0000)]
Remove the cached little endian variable. We can get it easily off
of the DataLayout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210555 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoHave AArch64SelectionDAGInfo take a DataLayout parameter rather
Eric Christopher [Tue, 10 Jun 2014 18:06:28 +0000 (18:06 +0000)]
Have AArch64SelectionDAGInfo take a DataLayout parameter rather
than a TargetMachine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210554 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove caching of the subtarget for AArch64SelectionDAGInfo.
Eric Christopher [Tue, 10 Jun 2014 18:06:25 +0000 (18:06 +0000)]
Remove caching of the subtarget for AArch64SelectionDAGInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210553 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMove DataLayout onto the AArch64 subtarget.
Eric Christopher [Tue, 10 Jun 2014 18:06:23 +0000 (18:06 +0000)]
Move DataLayout onto the AArch64 subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210552 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTest commit, wraps some lines to fit in 80 columns.
Zachary Turner [Tue, 10 Jun 2014 18:03:04 +0000 (18:03 +0000)]
Test commit, wraps some lines to fit in 80 columns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210551 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMove AArch64FrameLowering into the subtarget.
Eric Christopher [Tue, 10 Jun 2014 17:44:12 +0000 (17:44 +0000)]
Move AArch64FrameLowering into the subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210549 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove the uses of AArch64TargetMachine and AArch64Subtarget from
Eric Christopher [Tue, 10 Jun 2014 17:33:39 +0000 (17:33 +0000)]
Remove the uses of AArch64TargetMachine and AArch64Subtarget from
AArch64FrameLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210548 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoDo Materialize Floating Point in Mips Fast-Isel
Reed Kotler [Tue, 10 Jun 2014 16:45:44 +0000 (16:45 +0000)]
Do Materialize Floating Point in Mips Fast-Isel

Summary:
Implement materialize of floating point literals in Mips Fast-Isel

Reopened version of D3659

Test Plan: simplestorefp1.ll

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4071

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210546 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[X86] Improved target combine rules for selecting horizontal add/sub.
Andrea Di Biagio [Tue, 10 Jun 2014 16:42:57 +0000 (16:42 +0000)]
[X86] Improved target combine rules for selecting horizontal add/sub.

This patch slightly changes the algorithm introduced at revision 210477
to fix a problem where the algorithm was producing incorrect code for
the VEX.256 encoded versions of horizontal add/sub.

For these cases, we now try to split the two 256-bit vectors into
128-bit chunks before emitting horizontal add/sub dag nodes.

Added a new test case into haddsub-2.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210545 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoHexagon: Expand i1 SELECT_CC
Tom Stellard [Tue, 10 Jun 2014 16:42:41 +0000 (16:42 +0000)]
Hexagon: Expand i1 SELECT_CC

il is legal for Hexagon, so I should have marked this as Expand for
SELECT_CC when I removed setOperationAction(ISD::SELECT_CC, MVT::Other,
Expand); in r210541.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210544 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[X86] AVX512: Add vmovntdqa
Adam Nemet [Tue, 10 Jun 2014 16:39:53 +0000 (16:39 +0000)]
[X86] AVX512: Add vmovntdqa

Along with the corresponding intrinsic and tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210543 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix a bug in the Thumb1 ARM Load/Store optimizer
Renato Golin [Tue, 10 Jun 2014 16:39:21 +0000 (16:39 +0000)]
Fix a bug in the Thumb1 ARM Load/Store optimizer

Previously, the basic block was searched for future uses of the base register,
and if necessary any writeback to the base register was reset using a SUB
instruction (e.g. before calling a function) just before such a use. However,
this step happened *before* the merged LDM/STM instruction was built. So if
there was (e.g.) a function call directly after the not-yet-formed LDM/STM,
the pass would first insert a SUB instruction to reset the base register,
and then (at the same location, incorrectly) insert the LDM/STM itself.

This patch fixes PR19972. Patch by Moritz Roth.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210542 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoSelectionDAG: Don't use MVT::Other to determine legality of ISD::SELECT_CC
Tom Stellard [Tue, 10 Jun 2014 16:01:29 +0000 (16:01 +0000)]
SelectionDAG: Don't use MVT::Other to determine legality of ISD::SELECT_CC

The SelectionDAG bad a special case for ISD::SELECT_CC, where it would
allow targets to specify:

setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);

to indicate that they wanted to expand ISD::SELECT_CC for all types.
This wasn't applied correctly everywhere, and it makes writing new
DAG patterns with ISD::SELECT_CC difficult.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210541 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoSelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors
Tom Stellard [Tue, 10 Jun 2014 16:01:25 +0000 (16:01 +0000)]
SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors

This prevents a future commit from regressing:

test/CodeGen/R600/setcc-equivalent.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210540 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoSelectionDAG: Expand SELECT_CC to SELECT + SETCC
Tom Stellard [Tue, 10 Jun 2014 16:01:22 +0000 (16:01 +0000)]
SelectionDAG: Expand SELECT_CC to SELECT + SETCC

This consolidates code from the Hexagon, R600, and XCore targets.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210539 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PPC64LE] Recognize shufflevector patterns for little endian
Bill Schmidt [Tue, 10 Jun 2014 14:35:01 +0000 (14:35 +0000)]
[PPC64LE] Recognize shufflevector patterns for little endian

Various masks on shufflevector instructions are recognizable as
specific PowerPC instructions (vector pack, vector merge, etc.).
There is existing code in PPCISelLowering.cpp to recognize the correct
patterns for big endian code.  The masks for these instructions are
different for little endian code due to the big-endian numbering
employed by these instructions.  This patch adds the recognition code
for little endian.

I've added a new test case test/CodeGen/PowerPC/vec_shuffle_le.ll for
this.  The existing recognizer test (vec_shuffle.ll) is unnecessarily
verbose and difficult to read, so I felt it was better to add a new
test rather than modify the old one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210536 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[AArch64] Emit .ident compiler version attribute.
Chad Rosier [Tue, 10 Jun 2014 14:32:08 +0000 (14:32 +0000)]
[AArch64] Emit .ident compiler version attribute.
Patch by Ana Pazos<apazos@codeaurora.org>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210535 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdd detection of OS X relocatable SDK to compiler-rt as a lit.util function
Alexander Potapenko [Tue, 10 Jun 2014 14:22:00 +0000 (14:22 +0000)]
Add detection of OS X relocatable SDK to compiler-rt as a lit.util function

Clang's lit cfg already detects the currently selected SDK via
"xcrun --show-sdk-path". The same thing should be done for compiler-rt tests,
to make them work on recent OS X versions. Instead of duplicating the detection
code, this patch extracts the detection function into a lit.util method.

Patch by Kuba Brecka (kuba.brecka@gmail.com),
reviewed at http://reviews.llvm.org/D4072

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210534 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoCondition codes AL and NV are invalid in the aliases that use
Artyom Skrobov [Tue, 10 Jun 2014 13:11:35 +0000 (13:11 +0000)]
Condition codes AL and NV are invalid in the aliases that use
inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM).

Matching aliases based on "immediate classes", when disassembling,
wasn't previously supported, hence adding MCOperandPredicate
into class Operand, and implementing the support for it
in AsmWriterEmitter.

The parsing for those aliases was already custom, so just adding
the missing condition into AArch64AsmParser::parseCondCode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210528 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRefactoring in AsmWriterEmitter::EmitPrintAliasInstruction()
Artyom Skrobov [Tue, 10 Jun 2014 12:47:23 +0000 (12:47 +0000)]
Refactoring in AsmWriterEmitter::EmitPrintAliasInstruction()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210527 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAnonymous definitions in foreach blocks triggered a 'def already exists'
Artyom Skrobov [Tue, 10 Jun 2014 12:41:14 +0000 (12:41 +0000)]
Anonymous definitions in foreach blocks triggered a 'def already exists'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210526 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAArch64: disallow x30 & x29 as the destination for indirect tail calls
Tim Northover [Tue, 10 Jun 2014 10:50:24 +0000 (10:50 +0000)]
AArch64: disallow x30 & x29 as the destination for indirect tail calls

As Ana Pazos pointed out, these have to be restored to their incoming values
before a function returns; i.e. before the tail call. So they can't be used
correctly as the destination register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210525 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert "X86: elide comparisons after cmpxchg instructions."
Tim Northover [Tue, 10 Jun 2014 10:50:11 +0000 (10:50 +0000)]
Revert "X86: elide comparisons after cmpxchg instructions."

This reverts commit r210523. It was committed prematurely without waiting for
review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210524 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoX86: elide comparisons after cmpxchg instructions.
Tim Northover [Tue, 10 Jun 2014 10:49:07 +0000 (10:49 +0000)]
X86: elide comparisons after cmpxchg instructions.

The C++ and C semantics of the compare_and_swap operations actually
require us to return a boolean "success" value. In LLVM terms this
means a second comparison of the output of "cmpxchg" against the input
desired value.

However, x86's "cmpxchg" instruction sets all flags for the comparison
formed, so we can skip any secondary comparison. (N.b. this isn't true
for cmpxchg8b/16b, which only set ZF).

rdar://problem/13201607

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210523 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAArch64: teach FastISel how to handle offset FrameIndices
Tim Northover [Tue, 10 Jun 2014 09:52:44 +0000 (09:52 +0000)]
AArch64: teach FastISel how to handle offset FrameIndices

Previously we were abandonning the attempt, leading to some combination of
extra work (when selection of a load/store fails completely) and inferior code
(when this leads to a real memcpy call instead of inlining).

rdar://problem/17187463

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210520 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAArch64: make FastISel memcpy emission more robust.
Tim Northover [Tue, 10 Jun 2014 09:52:40 +0000 (09:52 +0000)]
AArch64: make FastISel memcpy emission more robust.

We were hitting an assert if FastISel couldn't create the load or store we
requested. Currently this happens for large frame-local addresses, though
CodeGen could be improved there.

rdar://problem/17187463

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210519 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoDelete X86JITInfo in the subtarget destructor.
Eric Christopher [Tue, 10 Jun 2014 08:03:42 +0000 (08:03 +0000)]
Delete X86JITInfo in the subtarget destructor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210516 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[llvm-readobj][ELF] Factor out the code retrieve ELF symbol information
Simon Atanasyan [Tue, 10 Jun 2014 05:59:15 +0000 (05:59 +0000)]
[llvm-readobj][ELF] Factor out the code retrieve ELF symbol information
(section name, section index, full name) into the separate functions.

No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210509 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoSmallVectorTest.cpp: Use LLVM_DELETED_FUNCTION.
NAKAMURA Takumi [Tue, 10 Jun 2014 04:06:56 +0000 (04:06 +0000)]
SmallVectorTest.cpp: Use LLVM_DELETED_FUNCTION.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210507 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[ConstantHoisting][X86] Improve the cost model for small constants with large types...
Juergen Ributzka [Tue, 10 Jun 2014 00:32:29 +0000 (00:32 +0000)]
[ConstantHoisting][X86] Improve the cost model for small constants with large types (i64 and above).

This improves the X86 cost model for small constants with large types. Before
this commit we would even hoist trivial constants such as i96 2.

This is related to <rdar://problem/17070936>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210504 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoReorder Value and User fields to save 8 bytes of padding on 64-bit
Reid Kleckner [Mon, 9 Jun 2014 23:32:20 +0000 (23:32 +0000)]
Reorder Value and User fields to save 8 bytes of padding on 64-bit

Reviewered by: rafael

Differential Revision: http://reviews.llvm.org/D4073

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210501 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemoving an "if (!this)" check from two print methods. The condition will
Richard Trieu [Mon, 9 Jun 2014 22:53:16 +0000 (22:53 +0000)]
Removing an "if (!this)" check from two print methods.  The condition will
never be true in a well-defined context.  The checking for null pointers
has been moved into the caller logic so it does not rely on undefined behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210497 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoReduce verbiage of lit.local.cfg files
Alp Toker [Mon, 9 Jun 2014 22:42:55 +0000 (22:42 +0000)]
Reduce verbiage of lit.local.cfg files

We can just split targets_to_build in one place and make it immutable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210496 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoSmallVector: support resize(N) with move-only types
David Blaikie [Mon, 9 Jun 2014 22:26:20 +0000 (22:26 +0000)]
SmallVector: support resize(N) with move-only types

Unfortunately there's no way to elegantly do this with pre-canned
algorithms. Using a generating iterator doesn't work because you default
construct for each element, then move construct into the actual slot
(bad for copy but non-movable types, and a little unneeded overhead even
in the move-only case), so just write it out manually.

This solution isn't exception safe (if one of the element's ctors calls
we don't fall back, destroy the constructed elements, and throw on -
which std::uninitialized_fill does do) but SmallVector (and LLVM) isn't
exception safe anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210495 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PPC64LE] Generate correct code for unaligned little-endian vector loads
Bill Schmidt [Mon, 9 Jun 2014 22:00:52 +0000 (22:00 +0000)]
[PPC64LE] Generate correct code for unaligned little-endian vector loads

The code in PPCTargetLowering::PerformDAGCombine() that handles
unaligned Altivec vector loads generates a lvsl followed by a vperm.
As we've seen in numerous other places, the vperm instruction has a
big-endian bias, and this is fixed for little endian by complementing
the permute control vector and swapping the input operands.  In this
case the lvsl is providing the permute control vector.  Rather than
generating an lvsl and a complement operation, it is sufficient to
generate an lvsr instruction instead.  Thus for LE code generation we
will generate an lvsr rather than an lvsl, and swap the other input
arguments on the vperm.

The existing test/CodeGen/PowerPC/vec_misalign.ll is updated to test
the code generation for PPC64 and PPC64LE, in addition to the existing
PPC32/G5 testing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210493 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoGenerate better location ranges for some register-described variables.
Alexey Samsonov [Mon, 9 Jun 2014 21:53:47 +0000 (21:53 +0000)]
Generate better location ranges for some register-described variables.

Don't terminate location ranges for register-described variables
at the end of machine basic block if this register is never modified
in the function body, except for the prologue and epilogue. Prologue
location is guessed by FrameSetup flags on MachineInstructions, while
epilogue location is deduced from debug locations of instructions
in the basic blocks ending with return instructions.

This patch is mostly targeted to fix non-trivial debug locations for
variables addressed via stack and frame pointers.

It is not really a generic fix. We can still produce poor debug info
for register-described variables if this register *is* modified somewhere
in the function, but in unrelated places. This might be the case for the debug
info in optimized binaries (e.g. for local variables in inlined functions).
LiveDebugVariables pass in CodeGen attempts to fix this problem by adjusting
DBG_VALUE instructions, but this pass is tied to greedy register allocator,
which is used in optimized builds only. Proper fix would likely involve
generalizing LiveDebugVariables to all register allocators. See more discussion
in http://reviews.llvm.org/D3933 review thread.

I'm proceeding with this patch to fix immediate severe problems and
important cases, e.g. fix completely broken debug info with AddressSanitizer
and fix PR19307 (missing debug info for by-value std::string arguments).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210492 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoUpdate langref for unnamed_addr being allowed in aliases.
Rafael Espindola [Mon, 9 Jun 2014 21:21:33 +0000 (21:21 +0000)]
Update langref for unnamed_addr being allowed in aliases.

Thanks to Duncan P. N. Exon Smith and Owen Anderson for noticing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210490 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoARM: add VLA extension for WoA Itanium ABI
Saleem Abdulrasool [Mon, 9 Jun 2014 20:18:42 +0000 (20:18 +0000)]
ARM: add VLA extension for WoA Itanium ABI

The armv7-windows-itanium environment is nearly identical to the MSVC ABI. It
has a few divergences, mostly revolving around the use of the Itanium ABI for
C++. VLA support is one of the extensions that are amongst the set of the
extensions.

This adds support for proper VLA emission for this environment. This is
somewhat similar to the handling for __chkstk emission on X86 and the large
stack frame emission for ARM. The invocation style for chkstk is still
controlled via the -mcmodel flag to clang.

Make an explicit note that this is an extension.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210489 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoLook through addrspacecasts when turning ptr comparisons into
Matt Arsenault [Mon, 9 Jun 2014 19:20:29 +0000 (19:20 +0000)]
Look through addrspacecasts when turning ptr comparisons into
index comparisons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210488 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdded functions cross-reference test.
Stepan Dyatkovskiy [Mon, 9 Jun 2014 19:03:02 +0000 (19:03 +0000)]
Added functions cross-reference test.
Originally this similar was initiated by Björn Steinbrink here:
http://reviews.llvm.org/D3437

Bug itself has been fixed by principal changes in MergeFunctions. Though
special checks for functions merging are still actual. And the test has
been accepted with slight modifications.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210486 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove old fenv.h workaround for a historic clang driver bug
Alp Toker [Mon, 9 Jun 2014 19:00:52 +0000 (19:00 +0000)]
Remove old fenv.h workaround for a historic clang driver bug

Tested and works fine with clang using libstdc++.

All indications are that this was fixed some time ago and isn't a problem with
any clang version we support.

I've added a note in PR6907 which is still open for some reason.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210485 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFold FEnv.h into the implementation
Alp Toker [Mon, 9 Jun 2014 18:28:53 +0000 (18:28 +0000)]
Fold FEnv.h into the implementation

Support headers shouldn't use config.h definitions, and they should never be
undefined like this.

ConstantFolding.cpp was the only user of this facility and already includes
config.h for other math features, so it makes sense to move the checks there at
point of use.

(The implicit config.h was also quite dangerous -- removing the FEnv.h include
would have silently disabled math constant folding without causing any tests to
fail. Need to investigate -Wundef once the cleanup is done.)

This eliminates the last config.h include from LLVM headers, paving the way for
more consistent configuration checks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210483 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[OCaml] Add more Llvm_target tests
Peter Zotov [Mon, 9 Jun 2014 18:28:47 +0000 (18:28 +0000)]
[OCaml] Add more Llvm_target tests

Patch by Jacques-Pascal Deplaix

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210482 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[OCaml] Unbreak Llvm_target.TargetMachine.set_verbose_asm
Peter Zotov [Mon, 9 Jun 2014 17:34:34 +0000 (17:34 +0000)]
[OCaml] Unbreak Llvm_target.TargetMachine.set_verbose_asm

Patch by Jacques-Pascal Deplaix

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210480 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMove all of the x86 subtarget initialized variables down into the x86 subtarget
Eric Christopher [Mon, 9 Jun 2014 17:08:19 +0000 (17:08 +0000)]
Move all of the x86 subtarget initialized variables down into the x86 subtarget
from the x86 target machine. Should be no functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210479 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600/SI: Rename VOP3 helper class to be more general
Matt Arsenault [Mon, 9 Jun 2014 17:00:46 +0000 (17:00 +0000)]
R600/SI: Rename VOP3 helper class to be more general

It has other uses besides shift instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210478 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[X86] Add target combine rules for horizontal add/sub.
Andrea Di Biagio [Mon, 9 Jun 2014 16:54:41 +0000 (16:54 +0000)]
[X86] Add target combine rules for horizontal add/sub.

This patch adds new target specific combine rules to identify horizontal
add/sub idioms from BUILD_VECTOR dag nodes.

This patch also teaches the DAGCombiner how to canonicalize sequences of
insert_vector_elt dag nodes according to the following rule:

  (insert_vector_elt (insert_vector_elt A, I0), I1) ->
    (insert_vecto_elt (insert_vector_elt A, I1), I0)

This new canonicalization rule only triggers if the inner insert_vector
dag node has exactly one use; also, both indices must be known constants,
and I1 < I0.
This last rule made it possible to write a simpler algorithm to identify
horizontal add/sub patterns because now we don't have to worry about the
ordering of insert_vector_elt dag nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210477 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600/SI: Keep 64-bit not on SALU
Matt Arsenault [Mon, 9 Jun 2014 16:36:31 +0000 (16:36 +0000)]
R600/SI: Keep 64-bit not on SALU

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210476 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600: Fix selection failure for vector bswap
Matt Arsenault [Mon, 9 Jun 2014 16:20:25 +0000 (16:20 +0000)]
R600: Fix selection failure for vector bswap

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210475 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[PPC64LE] Generate correct little-endian code for v16i8 multiply
Bill Schmidt [Mon, 9 Jun 2014 16:06:29 +0000 (16:06 +0000)]
[PPC64LE] Generate correct little-endian code for v16i8 multiply

The existing code in PPCTargetLowering::LowerMUL() for multiplying two
v16i8 values assumes that vector elements are numbered in big-endian
order.  For little-endian targets, the vector element numbering is
reversed, but the vmuleub, vmuloub, and vperm instructions still
assume big-endian numbering.  To account for this, we must adjust the
permute control vector and reverse the order of the input registers on
the vperm instruction.

The existing test/CodeGen/PowerPC/vec_mul.ll is updated to be executed
on powerpc64 and powerpc64le targets as well as the original powerpc
(32-bit) target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210474 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix test in r210472.
Evgeniy Stepanov [Mon, 9 Jun 2014 14:48:53 +0000 (14:48 +0000)]
Fix test in r210472.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210473 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[msan] Workaround for invalid origins in shufflevector.
Evgeniy Stepanov [Mon, 9 Jun 2014 14:29:34 +0000 (14:29 +0000)]
[msan] Workaround for invalid origins in shufflevector.

Makes origin propagation ignore literal undef operands, and,
in general, any operand we don't have origin for.

https://code.google.com/p/memory-sanitizer/issues/detail?id=56

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210472 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agollvm/test/CodeGen/X86/2014-05-29-factorial.ll: Relax an expression to match Win32...
NAKAMURA Takumi [Mon, 9 Jun 2014 14:20:23 +0000 (14:20 +0000)]
llvm/test/CodeGen/X86/2014-05-29-factorial.ll: Relax an expression to match Win32 x64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210471 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[mips] Fix a bug for NaCl target - Don't report the error when non-dangerous
Sasa Stankovic [Mon, 9 Jun 2014 14:09:28 +0000 (14:09 +0000)]
[mips] Fix a bug for NaCl target - Don't report the error when non-dangerous
load/store is in branch delay slot.

Differential Revision: http://llvm-reviews.chandlerc.com/D4048

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210470 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[X86] Avoid emitting unnecessary test instructions.
Andrea Di Biagio [Mon, 9 Jun 2014 12:34:50 +0000 (12:34 +0000)]
[X86] Avoid emitting unnecessary test instructions.

This patch teaches the backend how to check for the 'NoSignedWrap' flag on
binary operations to improve the emission of 'test' instructions.

If the result of a binary operation is known not to overflow we know that
resetting the Overflow flag is unnecessary and so we can avoid emitting
the test instruction.

Patch by Marcello Maggioni.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210468 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[DAG] Expose NoSignedWrap, NoUnsignedWrap and Exact flags to SelectionDAG.
Andrea Di Biagio [Mon, 9 Jun 2014 12:32:53 +0000 (12:32 +0000)]
[DAG] Expose NoSignedWrap, NoUnsignedWrap and Exact flags to SelectionDAG.

This patch modifies SelectionDAGBuilder to construct SDNodes with associated
NoSignedWrap, NoUnsignedWrap and Exact flags coming from IR BinaryOperator
instructions.

Added a new SDNode type called 'BinaryWithFlagsSDNode' to allow accessing
nsw/nuw/exact flags during codegen.

Patch by Marcello Maggioni.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210467 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[X86] Use ADD/SUB instead of INC/DEC for Silvermont
Alexey Volkov [Mon, 9 Jun 2014 11:40:41 +0000 (11:40 +0000)]
[X86] Use ADD/SUB instead of INC/DEC for Silvermont

According to Intel Software Optimization Manual
on Silvermont INC or DEC instructions require
an additional uop to merge the flags.
As a result, a branch instruction depending
on an INC or a DEC instruction incurs a 1 cycle penalty.

Differential Revision: http://reviews.llvm.org/D3990

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210466 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[AArch64] Missing aliases for CMP/CMN [W]SP with no shift
Artyom Skrobov [Mon, 9 Jun 2014 11:10:14 +0000 (11:10 +0000)]
[AArch64] Missing aliases for CMP/CMN [W]SP with no shift

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210464 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[docs] Fix typo, align comments, fix syntax highlighting
Jeroen Ketema [Mon, 9 Jun 2014 10:12:29 +0000 (10:12 +0000)]
[docs] Fix typo, align comments, fix syntax highlighting

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210462 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[mips][mips64r6] Add LDPC instruction
Zoran Jovanovic [Mon, 9 Jun 2014 09:49:51 +0000 (09:49 +0000)]
[mips][mips64r6] Add LDPC instruction
Differential Revision: http://reviews.llvm.org/D3822

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210460 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix line numbers for code inlined from __nodebug__ functions.
Evgeniy Stepanov [Mon, 9 Jun 2014 09:09:19 +0000 (09:09 +0000)]
Fix line numbers for code inlined from __nodebug__ functions.

Instructions from __nodebug__ functions don't have file:line
information even when inlined into no-nodebug functions. As a result,
intrinsics (SSE and other) from <*intrin.h> clang headers _never_
have file:line information.

With this change, an instruction without !dbg metadata gets one from
the call instruction when inlined.

Fixes PR19001.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210459 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[msan] Fix vector pack intrinsic handling.
Evgeniy Stepanov [Mon, 9 Jun 2014 08:40:16 +0000 (08:40 +0000)]
[msan] Fix vector pack intrinsic handling.

This fixes a crash on MMX intrinsics, as well as a corner case in handling of
all unsigned pack intrinsics.

PR19953.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210454 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoR600: Add more and testcases
Matt Arsenault [Mon, 9 Jun 2014 08:36:53 +0000 (08:36 +0000)]
R600: Add more and testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210453 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix gcc warning (enumeral and non-enumeral type in conditional expression)
Patrik Hagglund [Mon, 9 Jun 2014 07:35:07 +0000 (07:35 +0000)]
Fix gcc warning (enumeral and non-enumeral type in conditional expression)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210450 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[AArch64] Fix the ordering of the accumulate operand in SchedRW list.
Chad Rosier [Mon, 9 Jun 2014 01:54:00 +0000 (01:54 +0000)]
[AArch64] Fix the ordering of the accumulate operand in SchedRW list.
Patch by Dave Estes <cestes@codeaurora.org>
http://reviews.llvm.org/D4037

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210446 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[AArch64] When combining constant mul of power of 2 plus/minus 1, prefer shift
Chad Rosier [Mon, 9 Jun 2014 01:25:51 +0000 (01:25 +0000)]
[AArch64] When combining constant mul of power of 2 plus/minus 1, prefer shift
plus add.  The shift can be folded into the add.  This only effects codegen
when the constant is 3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210445 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[SeparateConstOffsetFromGEP] inbounds zext => sext for better splitting
Jingyue Wu [Sun, 8 Jun 2014 23:49:34 +0000 (23:49 +0000)]
[SeparateConstOffsetFromGEP] inbounds zext => sext for better splitting

For each array index that is in the form of zext(a), convert it to sext(a)
if we can prove zext(a) <= max signed value of typeof(a). The conversion
helps to split zext(x + y) into sext(x) + sext(y).

Reviewed in http://reviews.llvm.org/D4060

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210444 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoEscape "@function" with \verbatim. [-Wdocumentation]
NAKAMURA Takumi [Sun, 8 Jun 2014 23:25:02 +0000 (23:25 +0000)]
Escape "@function" with \verbatim. [-Wdocumentation]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210443 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[C++11] Use 'nullptr'.
Craig Topper [Sun, 8 Jun 2014 22:29:17 +0000 (22:29 +0000)]
[C++11] Use 'nullptr'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210442 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[SeparateConstOffsetFromGEP] Fix an illegitimate optimization on zext
Jingyue Wu [Sun, 8 Jun 2014 20:19:38 +0000 (20:19 +0000)]
[SeparateConstOffsetFromGEP] Fix an illegitimate optimization on zext

zext(a + b) != zext(a) + zext(b) even if a + b >= 0 && b >= 0.

e.g., a = i4 0b1111, b = i4 0b0001
zext a + b to i8 = zext 0b0000 to i8 = 0b00000000
(zext a to i8) + (zext b to i8) = 0b00001111 + 0b00000001 = 0b00010000

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210439 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRefactor canonicalizing array indices to a helper function
Jingyue Wu [Sun, 8 Jun 2014 20:15:45 +0000 (20:15 +0000)]
Refactor canonicalizing array indices to a helper function

No functionality changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210438 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[SeparateConstOffsetFromGEP] make two tests more strict
Jingyue Wu [Sun, 8 Jun 2014 20:01:42 +0000 (20:01 +0000)]
[SeparateConstOffsetFromGEP] make two tests more strict

inbounds are not necessary in these two tests. zext(a +nuw b) = zext(a) +
zext(b) should hold with or without inbounds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210437 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoSmallVector: Improve test coverage for insert with repetition
David Blaikie [Sun, 8 Jun 2014 19:33:40 +0000 (19:33 +0000)]
SmallVector: Improve test coverage for insert with repetition

To test cases that involve actual repetition (> 1 elements), at least
one element before the insertion point, and some elements of the
original range that still fit in that range space after insertion.

Actually we need coverage for the inverse case too (where no elements
after the insertion point fit into the previously allocated space), but
this'll do for now, and I might end up rewriting bits of SmallVector to
avoid that special case anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210436 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoScalarEvolution: Derive element size from the type of the loaded element
Tobias Grosser [Sun, 8 Jun 2014 19:21:20 +0000 (19:21 +0000)]
ScalarEvolution: Derive element size from the type of the loaded element

Before, we where looking at the size of the pointer type that specifies the
location from which to load the element. This did not make any sense at all.

This change fixes a bug in the delinearization where we failed to delinerize
certain load instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210435 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoSmallVector: More movable improvements - don't copy elements to make space when inser...
David Blaikie [Sun, 8 Jun 2014 19:12:31 +0000 (19:12 +0000)]
SmallVector: More movable improvements - don't copy elements to make space when inserting repeated elements.

Also split and improve tests a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210433 91177308-0d34-0410-b5e6-96231b3b80d8