oota-llvm.git
12 years agoSet the default PPC node scheduling preference to ILP (for the embedded cores).
Hal Finkel [Sun, 1 Apr 2012 19:23:08 +0000 (19:23 +0000)]
Set the default PPC node scheduling preference to ILP (for the embedded cores).

The 440 and A2 cores have detailed itineraries, and this allows them to be
fully used to maximize throughput.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153845 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd ppc440 itin. entries for LdStSTD*
Hal Finkel [Sun, 1 Apr 2012 19:23:04 +0000 (19:23 +0000)]
Add ppc440 itin. entries for LdStSTD*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153844 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse full anti-dep. breaking with post-ra sched. on the embedded ppc cores.
Hal Finkel [Sun, 1 Apr 2012 19:22:57 +0000 (19:22 +0000)]
Use full anti-dep. breaking with post-ra sched. on the embedded ppc cores.

Post-RA scheduling gives a significant performance improvement on
the embedded cores, so turn it on. Using full anti-dep. breaking is
important for FP-intensive blocks, so turn it on (just on the
embedded cores for now; this should also be good on the 970s because
post-ra scheduling is all that we have for now, but that should have
more testing first).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153843 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd instruction itinerary for the PPC64 A2 core.
Hal Finkel [Sun, 1 Apr 2012 19:22:40 +0000 (19:22 +0000)]
Add instruction itinerary for the PPC64 A2 core.

This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse SequenceToOffsetTable to create instruction name table. Saves space particularly...
Craig Topper [Sun, 1 Apr 2012 18:14:14 +0000 (18:14 +0000)]
Use SequenceToOffsetTable to create instruction name table. Saves space particularly on X86 where AVX instructions just add a 'v' to the front of other instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153841 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEmit the LLVM<->DWARF register mapping as a sorted table and use binary search to...
Benjamin Kramer [Sun, 1 Apr 2012 14:23:58 +0000 (14:23 +0000)]
Emit the LLVM<->DWARF register mapping as a sorted table and use binary search to do the lookup.

This also avoids emitting the information twice, which led to code bloat. On i386-linux-Release+Asserts
with all targets built this change shaves a whopping 1.3 MB off clang. The number is probably exaggerated
by recent inliner changes but the methods were already enormous with the old inline cost computation.

The DWARF reg -> LLVM reg mapping doesn't seem to have holes in it, so it could be a simple lookup table.
I didn't implement that optimization yet to avoid potentially changing functionality.

There is still some duplication both in tablegen and the generated code that should be cleaned up eventually.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153837 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoBelatedly address some code review from Chris.
Chandler Carruth [Sun, 1 Apr 2012 10:41:24 +0000 (10:41 +0000)]
Belatedly address some code review from Chris.

As a side note, I really dislike array_pod_sort... Do we really still
care about any STL implementations that get this so wrong? Does libc++?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153834 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd some more testing to cover the remaining two cases where
Chandler Carruth [Sun, 1 Apr 2012 10:36:17 +0000 (10:36 +0000)]
Add some more testing to cover the remaining two cases where
always-inlining is disabled: recursive functions and indirectbr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153833 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix a pretty scary bug I introduced into the always inliner with
Chandler Carruth [Sun, 1 Apr 2012 10:21:05 +0000 (10:21 +0000)]
Fix a pretty scary bug I introduced into the always inliner with
a single missing character. Somehow, this had gone untested. I've added
tests for returns-twice logic specifically with the always-inliner that
would have caught this, and fixed the bug.

Thanks to Matt for the careful review and spotting this!!! =D

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153832 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoReplace four tiny tests with various uses of grep and not with a single
Chandler Carruth [Sun, 1 Apr 2012 10:11:17 +0000 (10:11 +0000)]
Replace four tiny tests with various uses of grep and not with a single
test and FileCheck.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153831 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agomisched: Add finalizeScheduler to complete the target interface.
Andrew Trick [Sun, 1 Apr 2012 07:24:23 +0000 (07:24 +0000)]
misched: Add finalizeScheduler to complete the target interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153827 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRemoving a file that's no longer being used after the recent refactorings
Eli Bendersky [Sun, 1 Apr 2012 06:50:01 +0000 (06:50 +0000)]
Removing a file that's no longer being used after the recent refactorings

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153825 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSplit the LdStGeneral PPC itin. class into LdStLoad and LdStStore.
Hal Finkel [Sun, 1 Apr 2012 04:44:16 +0000 (04:44 +0000)]
Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore.

Loads and stores can have different pipeline behavior, especially on
embedded chips. This change allows those differences to be expressed.
Except for the 440 scheduler, there are no functionality changes.
On the 440, the latency adjustment is only by one cycle, and so this
probably does not affect much. Nevertheless, it will make a larger
difference in the future and this removes a FIXME from the 440 itin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153821 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd a workaround for building with old versions of clang.
Rafael Espindola [Sat, 31 Mar 2012 21:54:20 +0000 (21:54 +0000)]
Add a workaround for building with old versions of clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153820 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd a triple to the test.
Rafael Espindola [Sat, 31 Mar 2012 18:59:07 +0000 (18:59 +0000)]
Add a triple to the test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153818 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTeach CodeGen's version of computeMaskedBits to understand the range metadata.
Rafael Espindola [Sat, 31 Mar 2012 18:14:00 +0000 (18:14 +0000)]
Teach CodeGen's version of computeMaskedBits to understand the range metadata.
This is the CodeGen equivalent of r153747. I tested that there is not noticeable
performance difference with any combination of -O0/-O2 /-g when compiling
gcc as a single compilation unit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153817 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix dynamic linking on PPC64.
Hal Finkel [Sat, 31 Mar 2012 14:45:15 +0000 (14:45 +0000)]
Fix dynamic linking on PPC64.

Dynamic linking on PPC64 has had problems since we had to move the top-down
hazard-detection logic post-ra. For dynamic linking to work there needs to be
a nop placed after every call. It turns out that it is really hard to guarantee
that nothing will be placed in between the call (bl) and the nop during post-ra
scheduling. Previous attempts at fixing this by placing logic inside the
hazard detector only partially worked.

This is now fixed in a different way: call+nop codegen-only instructions. As far
as CodeGen is concerned the pair is now a single instruction and cannot be split.
This solution works much better than previous attempts.

The scoreboard hazard detector is also renamed to be more generic, there is currently
no cpu-specific logic in it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153816 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix a typo reported in IRC by someone reviewing this code.
Chandler Carruth [Sat, 31 Mar 2012 13:18:09 +0000 (13:18 +0000)]
Fix a typo reported in IRC by someone reviewing this code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153815 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoGive the always-inliner its own custom filter. It shouldn't have to pay
Chandler Carruth [Sat, 31 Mar 2012 13:17:18 +0000 (13:17 +0000)]
Give the always-inliner its own custom filter. It shouldn't have to pay
the very high overhead of the complex inline cost analysis when all it
wants to do is detect three patterns which must not be inlined. Comment
the code, clean it up, and leave some hints about possible performance
improvements if this ever shows up on a profile.

Moving this off of the (now more expensive) inline cost analysis is
particularly important because we have to run this inliner even at -O0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153814 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRemove a bunch of empty, dead, and no-op methods from all of these
Chandler Carruth [Sat, 31 Mar 2012 12:48:08 +0000 (12:48 +0000)]
Remove a bunch of empty, dead, and no-op methods from all of these
interfaces. These methods were used in the old inline cost system where
there was a persistent cache that had to be updated, invalidated, and
cleared. We're now doing more direct computations that don't require
this intricate dance. Even if we resume some level of caching, it would
almost certainly have a simpler and more narrow interface than this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153813 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoInitial commit for the rewrite of the inline cost analysis to operate
Chandler Carruth [Sat, 31 Mar 2012 12:42:41 +0000 (12:42 +0000)]
Initial commit for the rewrite of the inline cost analysis to operate
on a per-callsite walk of the called function's instructions, in
breadth-first order over the potentially reachable set of basic blocks.

This is a major shift in how inline cost analysis works to improve the
accuracy and rationality of inlining decisions. A brief outline of the
algorithm this moves to:

- Build a simplification mapping based on the callsite arguments to the
  function arguments.
- Push the entry block onto a worklist of potentially-live basic blocks.
- Pop the first block off of the *front* of the worklist (for
  breadth-first ordering) and walk its instructions using a custom
  InstVisitor.
- For each instruction's operands, re-map them based on the
  simplification mappings available for the given callsite.
- Compute any simplification possible of the instruction after
  re-mapping, and store that back int othe simplification mapping.
- Compute any bonuses, costs, or other impacts of the instruction on the
  cost metric.
- When the terminator is reached, replace any conditional value in the
  terminator with any simplifications from the mapping we have, and add
  any successors which are not proven to be dead from these
  simplifications to the worklist.
- Pop the next block off of the front of the worklist, and repeat.
- As soon as the cost of inlining exceeds the threshold for the
  callsite, stop analyzing the function in order to bound cost.

The primary goal of this algorithm is to perfectly handle dead code
paths. We do not want any code in trivially dead code paths to impact
inlining decisions. The previous metric was *extremely* flawed here, and
would always subtract the average cost of two successors of
a conditional branch when it was proven to become an unconditional
branch at the callsite. There was no handling of wildly different costs
between the two successors, which would cause inlining when the path
actually taken was too large, and no inlining when the path actually
taken was trivially simple. There was also no handling of the code
*path*, only the immediate successors. These problems vanish completely
now. See the added regression tests for the shiny new features -- we
skip recursive function calls, SROA-killing instructions, and high cost
complex CFG structures when dead at the callsite being analyzed.

Switching to this algorithm required refactoring the inline cost
interface to accept the actual threshold rather than simply returning
a single cost. The resulting interface is pretty bad, and I'm planning
to do lots of interface cleanup after this patch.

Several other refactorings fell out of this, but I've tried to minimize
them for this patch. =/ There is still more cleanup that can be done
here. Please point out anything that you see in review.

I've worked really hard to try to mirror at least the spirit of all of
the previous heuristics in the new model. It's not clear that they are
all correct any more, but I wanted to minimize the change in this single
patch, it's already a bit ridiculous. One heuristic that is *not* yet
mirrored is to allow inlining of functions with a dynamic alloca *if*
the caller has a dynamic alloca. I will add this back, but I think the
most reasonable way requires changes to the inliner itself rather than
just the cost metric, and so I've deferred this for a subsequent patch.
The test case is XFAIL-ed until then.

As mentioned in the review mail, this seems to make Clang run about 1%
to 2% faster in -O0, but makes its binary size grow by just under 4%.
I've looked into the 4% growth, and it can be fixed, but requires
changes to other parts of the inliner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153812 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd support to the InstVisitor for visiting a generic callsite. The
Chandler Carruth [Sat, 31 Mar 2012 11:31:24 +0000 (11:31 +0000)]
Add support to the InstVisitor for visiting a generic callsite. The
visitor will now visit a CallInst and an InvokeInst with
instruction-specific visitors, then visit a generic CallSite visitor,
then delegate back to the Instruction visitor and the TerminatorInst
visitors depending on whether a call or an invoke originally. This will
be used in the soon-to-land inline cost rewrite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153811 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMove trivial functions into the class definition.
Bill Wendling [Sat, 31 Mar 2012 11:25:18 +0000 (11:25 +0000)]
Move trivial functions into the class definition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153810 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTrim headers.
Bill Wendling [Sat, 31 Mar 2012 11:22:30 +0000 (11:22 +0000)]
Trim headers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153809 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoIndent according to LLVM's style guide.
Bill Wendling [Sat, 31 Mar 2012 11:15:43 +0000 (11:15 +0000)]
Indent according to LLVM's style guide.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153808 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCleanup whitespace and trim some of the #includes.
Bill Wendling [Sat, 31 Mar 2012 11:10:35 +0000 (11:10 +0000)]
Cleanup whitespace and trim some of the #includes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153807 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoInternalize: Remove reference of @llvm.noinline, it was replaced with the noinline...
Benjamin Kramer [Sat, 31 Mar 2012 11:03:47 +0000 (11:03 +0000)]
Internalize: Remove reference of @llvm.noinline, it was replaced with the noinline attribute a long time ago.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153806 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoThese strings aren't 'const char *' but 'char *'.
Bill Wendling [Sat, 31 Mar 2012 10:51:45 +0000 (10:51 +0000)]
These strings aren't 'const char *' but 'char *'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153805 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCleanup whitespace.
Bill Wendling [Sat, 31 Mar 2012 10:50:14 +0000 (10:50 +0000)]
Cleanup whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153804 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFree the codegen options when deleting LTO code generator object.
Bill Wendling [Sat, 31 Mar 2012 10:49:43 +0000 (10:49 +0000)]
Free the codegen options when deleting LTO code generator object.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153803 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCleanup whitespace and remove unneeded 'extern' keyword on function definitions.
Bill Wendling [Sat, 31 Mar 2012 10:44:20 +0000 (10:44 +0000)]
Cleanup whitespace and remove unneeded 'extern' keyword on function definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153802 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoClean up the naming in this test. Someone pointed this out in review at
Chandler Carruth [Sat, 31 Mar 2012 10:38:48 +0000 (10:38 +0000)]
Clean up the naming in this test. Someone pointed this out in review at
one point, and I forgot to go back and clean it up. Sorry about that. =/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153801 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFileCheck-ize this test, and generally tidy it up prior to changing
Chandler Carruth [Sat, 31 Mar 2012 09:22:33 +0000 (09:22 +0000)]
FileCheck-ize this test, and generally tidy it up prior to changing
things around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153799 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoI noticed in passing that the Metadata getIfExists method was creating a new
Duncan Sands [Sat, 31 Mar 2012 08:20:11 +0000 (08:20 +0000)]
I noticed in passing that the Metadata getIfExists method was creating a new
node and returning it if one didn't exist.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153798 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCorrectly vectorize powi.
Hal Finkel [Sat, 31 Mar 2012 03:38:40 +0000 (03:38 +0000)]
Correctly vectorize powi.

The powi intrinsic requires special handling because it always takes a single
integer power regardless of the result type. As a result, we can vectorize
only if the powers are equal. Fixes PR12364.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153797 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agocomment typo
Andrew Trick [Sat, 31 Mar 2012 02:39:17 +0000 (02:39 +0000)]
comment typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153796 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSelect static relocation model if it is jitting.
Akira Hatanaka [Sat, 31 Mar 2012 02:38:36 +0000 (02:38 +0000)]
Select static relocation model if it is jitting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153795 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoIntroduce Register Units: Give each leaf register a number.
Andrew Trick [Sat, 31 Mar 2012 01:35:59 +0000 (01:35 +0000)]
Introduce Register Units: Give each leaf register a number.

First small step toward modeling multi-register multi-pressure. In the
future, register units can also be used to model liveness and
aliasing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153794 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd a 2 byte safety margin in offset computations.
Jakob Stoklund Olesen [Sat, 31 Mar 2012 00:06:44 +0000 (00:06 +0000)]
Add a 2 byte safety margin in offset computations.

ARMConstantIslandPass still has bugs where jump table compression can
cause constant pool entries to go out of range.

Add a safety margin of 2 bytes when placing constant islands, but use
the real max displacement for verification.

<rdar://problem/11156595>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153789 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd more debugging output to ARMConstantIslandPass.
Jakob Stoklund Olesen [Sat, 31 Mar 2012 00:06:42 +0000 (00:06 +0000)]
Add more debugging output to ARMConstantIslandPass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153788 91177308-0d34-0410-b5e6-96231b3b80d8

12 years ago* Set the scope attributes for the ASM symbol we added to be the value passed
Bill Wendling [Fri, 30 Mar 2012 23:26:06 +0000 (23:26 +0000)]
* Set the scope attributes for the ASM symbol we added to be the value passed
  into the function.
* Reorder some header files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153783 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRip out emission of the regIsInRegClass function for the asm printer.
Benjamin Kramer [Fri, 30 Mar 2012 23:13:40 +0000 (23:13 +0000)]
Rip out emission of the regIsInRegClass function for the asm printer.

It's slow, bloated and completely redundant with MCRegisterClass::contains.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153782 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM fix encoding fixup resolution for ldrd and friends.
Jim Grosbach [Fri, 30 Mar 2012 21:54:22 +0000 (21:54 +0000)]
ARM fix encoding fixup resolution for ldrd and friends.

The 8-bit payload is not contiguous in the opcode. Move the upper nibble
over 4 bits into the correct place.

rdar://11158641

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153780 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse SequenceToOffsetTable in emitRegisterNameString.
Jakob Stoklund Olesen [Fri, 30 Mar 2012 21:12:52 +0000 (21:12 +0000)]
Use SequenceToOffsetTable in emitRegisterNameString.

This allows suffix sharing in register names. (AX is a suffix of EAX).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153777 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoReapply 153764 and 153761 with a fix.
Jakob Stoklund Olesen [Fri, 30 Mar 2012 20:24:14 +0000 (20:24 +0000)]
Reapply 153764 and 153761 with a fix.

Use an explicit comparator instead of the default.

The sets are sorted, but not using the default comparator. Hopefully,
this will unbreak the Linux builders.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153772 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRevert 153764 and 153761. They broke a --enable-optimized --enable-assertions
Rafael Espindola [Fri, 30 Mar 2012 20:09:06 +0000 (20:09 +0000)]
Revert 153764 and 153761. They broke a --enable-optimized --enable-assertions
--enable-expensive-checks build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153771 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM assembler should prefer non-aliases encoding of cmp.
Jim Grosbach [Fri, 30 Mar 2012 19:59:02 +0000 (19:59 +0000)]
ARM assembler should prefer non-aliases encoding of cmp.

When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg,
we want to use the non-negated form to make sure we prefer the normal
encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153770 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM encoding for VSWP got the second operand incorrect.
Jim Grosbach [Fri, 30 Mar 2012 18:53:01 +0000 (18:53 +0000)]
ARM encoding for VSWP got the second operand incorrect.

Make the non-tied register operand names line up with what the base
class encoding handler expects.

rdar://11157236

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM can only use narrow encoding for low regs.
Jim Grosbach [Fri, 30 Mar 2012 18:39:43 +0000 (18:39 +0000)]
ARM can only use narrow encoding for low regs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153765 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCompress SimpleValueType lists by sharing.
Jakob Stoklund Olesen [Fri, 30 Mar 2012 17:42:04 +0000 (17:42 +0000)]
Compress SimpleValueType lists by sharing.

Many register classes have the same value types. Share the table space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153764 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCompress register lists by sharing suffixes.
Jakob Stoklund Olesen [Fri, 30 Mar 2012 17:25:43 +0000 (17:25 +0000)]
Compress register lists by sharing suffixes.

TableGen emits lists of sub-registers, super-registers, and overlaps. Put
them all in a single table and use a SequenceToOffsetTable to share
suffixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153761 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd a SequenceToOffsetTable to TableGen.
Jakob Stoklund Olesen [Fri, 30 Mar 2012 17:25:40 +0000 (17:25 +0000)]
Add a SequenceToOffsetTable to TableGen.

This is similar to the StringToOffsetTable we use to produce string
tables, but it can be used for other sequences than strings, and it
eliminates entries for suffixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153760 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM integrated assembler should encoding choice for add/sub imm.
Jim Grosbach [Fri, 30 Mar 2012 17:20:40 +0000 (17:20 +0000)]
ARM integrated assembler should encoding choice for add/sub imm.

For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2
can be used for this syntax. Prefer the narrow encoding when possible.

rdar://11156277

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoHandle unreachable code in the dominates functions. This changes users when
Rafael Espindola [Fri, 30 Mar 2012 16:46:21 +0000 (16:46 +0000)]
Handle unreachable code in the dominates functions. This changes users when
needed for correctness, but still doesn't clean up code that now unnecessary
checks for reachability.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153755 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRe-factored RuntimeDyLd:
Danil Malyshev [Fri, 30 Mar 2012 16:45:19 +0000 (16:45 +0000)]
Re-factored RuntimeDyLd:

1. The main works will made in the RuntimeDyLdImpl with uses the ObjectFile class. RuntimeDyLdMachO and RuntimeDyLdELF now only parses relocations and resolve it. This is allows to make improvements of the RuntimeDyLd more easily. In addition the support for COFF can be easily added.

2. Added ARM relocations to RuntimeDyLdELF.

3. Added support for stub functions for the ARM, allowing to do a long branch.

4. Added support for external functions that are not loaded from the object files, but can be loaded from external libraries. Now MCJIT can correctly execute the code containing the printf, putc, and etc.

5. The sections emitted instead functions, thanks Jim Grosbach. MemoryManager.startFunctionBody() and MemoryManager.endFunctionBody() have been removed.
6. MCJITMemoryManager.allocateDataSection() and MCJITMemoryManager. allocateCodeSection() used JMM->allocateSpace() instead of JMM->allocateCodeSection() and JMM->allocateDataSection(), because I got an error: "Cannot allocate an allocated block!" with object file contains more than one code or data sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153754 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM assembly parsing needs to be paranoid about negative immediates.
Jim Grosbach [Fri, 30 Mar 2012 16:31:31 +0000 (16:31 +0000)]
ARM assembly parsing needs to be paranoid about negative immediates.

Make sure to treat immediates as unsigned when doing relative comparisons.

rdar://11153621

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153753 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd computeMaskedBitsLoad back, as it was the change to instsimplify that
Rafael Espindola [Fri, 30 Mar 2012 15:52:11 +0000 (15:52 +0000)]
Add computeMaskedBitsLoad back, as it was the change to instsimplify that
caused the slowdown last time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153747 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd a note about a missed cmov -> sbb opportunity.
Benjamin Kramer [Fri, 30 Mar 2012 13:02:58 +0000 (13:02 +0000)]
Add a note about a missed cmov -> sbb opportunity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153741 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCleanup whitespace. Doxygenize comments. And indent to llvm coding standards.
Bill Wendling [Fri, 30 Mar 2012 10:29:38 +0000 (10:29 +0000)]
Cleanup whitespace. Doxygenize comments. And indent to llvm coding standards.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153740 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEnsure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.
James Molloy [Fri, 30 Mar 2012 09:15:32 +0000 (09:15 +0000)]
Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.

Patch by Tim Northover!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM target should allow codegenprep to duplicate ret instructions to enable tailcall...
Evan Cheng [Fri, 30 Mar 2012 01:24:39 +0000 (01:24 +0000)]
ARM target should allow codegenprep to duplicate ret instructions to enable tailcall opt. rdar://11140249

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153717 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTestcase for r153710.
Bill Wendling [Fri, 30 Mar 2012 00:26:54 +0000 (00:26 +0000)]
Testcase for r153710.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153711 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd testcase for r153705
Bill Wendling [Fri, 30 Mar 2012 00:05:02 +0000 (00:05 +0000)]
Add testcase for r153705

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153706 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoIf we have a VLA that has a "use" in a metadata node that's then used
Bill Wendling [Fri, 30 Mar 2012 00:02:55 +0000 (00:02 +0000)]
If we have a VLA that has a "use" in a metadata node that's then used
here but it has no other uses, then we have a problem. E.g.,

  int foo (const int *x) {
    char a[*x];
    return 0;
  }

If we assign 'a' a vreg and fast isel later on has to use the selection
DAG isel, it will want to copy the value to the vreg. However, there are
no uses, which goes counter to what selection DAG isel expects.
<rdar://problem/11134152>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153705 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoChange the constant in this testcase so that it results in a constant pool
Lang Hames [Thu, 29 Mar 2012 23:52:38 +0000 (23:52 +0000)]
Change the constant in this testcase so that it results in a constant pool
load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153704 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRevert r153694. It was causing failures in the buildbots.
Bill Wendling [Thu, 29 Mar 2012 23:23:59 +0000 (23:23 +0000)]
Revert r153694. It was causing failures in the buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153701 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoInvalidate liveness in ARMConstantIslandPass.
Jakob Stoklund Olesen [Thu, 29 Mar 2012 23:14:26 +0000 (23:14 +0000)]
Invalidate liveness in ARMConstantIslandPass.

This pass splits basic blocks to insert constant islands, and it
doesn't recompute the live-in lists. No later passes depend on accurate
liveness information.

This fixes PR12410 where the machine code verifier was complaining.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153700 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoPrefer even-odd D-register pairs.
Jakob Stoklund Olesen [Thu, 29 Mar 2012 22:54:32 +0000 (22:54 +0000)]
Prefer even-odd D-register pairs.

We are sometimes allocatinog from the DPair register class which
contains odd-even pairs in addition to the Q registers.

Place the Q registers first in the DPair allocation order as they can be
copied with a single instruction. The odd-even pairs should only be
allocated as a last resort.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153699 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFilecheck-ize this test so that it actually tests something reasonable.
Chandler Carruth [Thu, 29 Mar 2012 22:01:41 +0000 (22:01 +0000)]
Filecheck-ize this test so that it actually tests something reasonable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153697 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTry using vmov.i32 to materialize FP32 constants that can't be materialized by
Lang Hames [Thu, 29 Mar 2012 21:56:11 +0000 (21:56 +0000)]
Try using vmov.i32 to materialize FP32 constants that can't be materialized by
vmov.f32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153696 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRe-factored RuntimeDyld.
Danil Malyshev [Thu, 29 Mar 2012 21:46:18 +0000 (21:46 +0000)]
Re-factored RuntimeDyld.
Added ExecutionEngine/MCJIT tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153694 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoLowercase the tag name to match the rest of dwarf.
Eric Christopher [Thu, 29 Mar 2012 21:35:05 +0000 (21:35 +0000)]
Lowercase the tag name to match the rest of dwarf.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153691 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM assembly 'cmp lr, #0' should not encode using 'cmn'.
Jim Grosbach [Thu, 29 Mar 2012 21:19:52 +0000 (21:19 +0000)]
ARM assembly 'cmp lr, #0' should not encode using 'cmn'.

The CMP->CMN alias was matching for an immediate of zero when it
should only match for negative values.

rdar://11129224

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoThe shuffle scheduler is only available in asserts build - make misched-new.ll
Lang Hames [Thu, 29 Mar 2012 21:11:47 +0000 (21:11 +0000)]
The shuffle scheduler is only available in asserts build - make misched-new.ll
testcase require asserts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153687 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoHandle register copies for the new ARM register classes.
Jakob Stoklund Olesen [Thu, 29 Mar 2012 21:10:40 +0000 (21:10 +0000)]
Handle register copies for the new ARM register classes.

ARM recently gained DPair, DTriple, and DQuad register classes.
Update copyPhysReg() to handle copies in these register classes.

No test case, it is difficult to make the register allocator emit the
odd copies reliably. The missing DPair copy caused a failure on
partialsums in the nightly test suite.

<rdar://problem/11147997>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153686 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoDrop O4 from the llc manpage, it was removed in r70445.
Benjamin Kramer [Thu, 29 Mar 2012 20:40:18 +0000 (20:40 +0000)]
Drop O4 from the llc manpage, it was removed in r70445.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153684 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMake x86 REP_MOV* and REP_STO instructions use the correct operand sizes in 64-bit...
Lang Hames [Thu, 29 Mar 2012 19:54:28 +0000 (19:54 +0000)]
Make x86 REP_MOV* and REP_STO instructions use the correct operand sizes in 64-bit mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153680 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix missed files in JIT unittests Makefile
Danil Malyshev [Thu, 29 Mar 2012 18:53:15 +0000 (18:53 +0000)]
Fix missed files in JIT unittests Makefile

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153672 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoExpand FREM.
Akira Hatanaka [Thu, 29 Mar 2012 18:43:11 +0000 (18:43 +0000)]
Expand FREM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153671 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd more constness to CodeGenRegisters.
Jakob Stoklund Olesen [Thu, 29 Mar 2012 18:03:59 +0000 (18:03 +0000)]
Add more constness to CodeGenRegisters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153667 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoDon't PRE compares.
Jakob Stoklund Olesen [Thu, 29 Mar 2012 17:22:39 +0000 (17:22 +0000)]
Don't PRE compares.

CodeGenPrepare sinks compare instructions down to their uses to prevent
live flags and predicate registers across basic blocks.

PRE of a compare instruction prevents that, forcing the i1 compare
result into a general purpose register.  That is usually more expensive
than the redundant compare PRE was trying to eliminate in the first
place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153657 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoReplace assert(0) with llvm_unreachable to avoid warnings about dropping off the...
Benjamin Kramer [Thu, 29 Mar 2012 12:37:26 +0000 (12:37 +0000)]
Replace assert(0) with llvm_unreachable to avoid warnings about dropping off the end of a non-void function in Release builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153643 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd support for objc property decls according to the page at:
Eric Christopher [Thu, 29 Mar 2012 08:42:56 +0000 (08:42 +0000)]
Add support for objc property decls according to the page at:

http://llvm.org/docs/SourceLevelDebugging.html#objcproperty

including type and DECL. Expand the metadata needed accordingly.

rdar://11144023

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153639 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMake some headway towards compiling all of LLVM.
Bill Wendling [Thu, 29 Mar 2012 08:27:32 +0000 (08:27 +0000)]
Make some headway towards compiling all of LLVM.

Module-level ASM may contain definitions of functions and globals. However, we
were not telling the linker that these globals had definitions. As far as it was
concerned, they were just declarations.

Attempt to resolve this by inserting module-level ASM functions and globals into
the '_symbol' set so that the linker will know that they have values.

This gets us further towards our goal of compiling LLVM, but it still has
problems when linking libLTO.dylib because of the `-dead_strip' flag that's
passed to the linker.

<rdar://problem/11124216>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153638 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoOnly allow symbolic names for (v)cmpss/sd/ps/pd encodings 8-31 to be used with 'v...
Craig Topper [Thu, 29 Mar 2012 07:11:23 +0000 (07:11 +0000)]
Only allow symbolic names for (v)cmpss/sd/ps/pd encodings 8-31 to be used with 'v' version of instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153636 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFor X86, change load/dec-or-inc/store into dec-or-inc, respectively.
Joel Jones [Thu, 29 Mar 2012 05:45:48 +0000 (05:45 +0000)]
For X86, change load/dec-or-inc/store into dec-or-inc, respectively.

This is a code change to add support for changing instruction sequences of the form:

  load
  inc/dec of 8/16/32/64 bits
  store

into the appropriate X86 inc/dec through memory instruction:

  inc[qlwb] / dec[qlwb]

The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better
named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode.  The comments have also been expanded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153635 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCleanup whitespace.
Bill Wendling [Thu, 29 Mar 2012 04:28:00 +0000 (04:28 +0000)]
Cleanup whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153634 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCache the end() iterator.
Bill Wendling [Thu, 29 Mar 2012 03:34:57 +0000 (03:34 +0000)]
Cache the end() iterator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153632 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoReverted to revision 153616 to unblock build
Joel Jones [Thu, 29 Mar 2012 01:20:56 +0000 (01:20 +0000)]
Reverted to revision 153616 to unblock build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153623 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFor X86, change load/dec-or-inc/store into dec-or-inc, respectively.
Joel Jones [Thu, 29 Mar 2012 00:37:47 +0000 (00:37 +0000)]
For X86, change load/dec-or-inc/store into dec-or-inc, respectively.

This is a code change to add support for changing instruction sequences of the form:

  load
  inc/dec of 8/16/32/64 bits
  store

into the appropriate X86 inc/dec through memory instruction:

  inc[qlwb] / dec[qlwb]

The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better
named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode.  The comments have also been expanded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153617 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEnable machine code verification in the entire code generator.
Jakob Stoklund Olesen [Wed, 28 Mar 2012 23:54:28 +0000 (23:54 +0000)]
Enable machine code verification in the entire code generator.

Some targets still mess up the liveness information, but that isn't
verified after MRI->invalidateLiveness().

The verifier can still check other useful things like register classes
and CFG, so it should be enabled after all passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153615 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEnable machine code verification after PreSched2 passes.
Jakob Stoklund Olesen [Wed, 28 Mar 2012 23:31:15 +0000 (23:31 +0000)]
Enable machine code verification after PreSched2 passes.

The late scheduler depends on accurate liveness information if it is
breaking anti-dependencies, so we should be able to verify it.

Relax the terminator checking in the machine code verifier so it can
handle the basic blocks created by if conversion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153614 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCleanup some whitespaces.
Bill Wendling [Wed, 28 Mar 2012 23:12:18 +0000 (23:12 +0000)]
Cleanup some whitespaces.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153612 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoDon't kill the base register when expanding strd.
Jakob Stoklund Olesen [Wed, 28 Mar 2012 23:07:03 +0000 (23:07 +0000)]
Don't kill the base register when expanding strd.

When an strd instruction doesn't get the registers it wants, it can be
expanded into two str instructions. Make sure the first str doesn't kill
the base register in the case where the base and data registers are
identical:

  t2STRi12 %R0<kill>, %R0, 4, pred:14, pred:%noreg
  t2STRi12 %R2<kill>, %R0, 8, pred:14, pred:%noreg

<rdar://problem/11101911>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153611 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoPreserve implicit defs in ARMLoadStoreOptimizer.
Jakob Stoklund Olesen [Wed, 28 Mar 2012 22:50:56 +0000 (22:50 +0000)]
Preserve implicit defs in ARMLoadStoreOptimizer.

When a number of sub-register VLRDS instructions are combined into a
VLDM, preserve any super-register implicit defs. This is required to
keep the register scavenger and machine code verifier happy.

Enable machine code verification after ARMLoadStoreOptimizer.
ARM/2012-01-26-CopyPropKills.ll was failing because of this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153610 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTidy up. Whitespace.
Jim Grosbach [Wed, 28 Mar 2012 22:34:41 +0000 (22:34 +0000)]
Tidy up. Whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153609 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMove getPointerToNamedFunction() from JIT/MCJIT to JITMemoryManager.
Danil Malyshev [Wed, 28 Mar 2012 21:46:36 +0000 (21:46 +0000)]
Move getPointerToNamedFunction() from JIT/MCJIT to JITMemoryManager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153607 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoHandle intrinsics in GlobalsModRef. Fixes pr12351.
Rafael Espindola [Wed, 28 Mar 2012 21:31:24 +0000 (21:31 +0000)]
Handle intrinsics in GlobalsModRef. Fixes pr12351.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153604 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSpill DPair registers, not just QPR.
Jakob Stoklund Olesen [Wed, 28 Mar 2012 21:20:32 +0000 (21:20 +0000)]
Spill DPair registers, not just QPR.

The arm_neon intrinsics can create virtual registers from the DPair
register class which allows both even-odd and odd-even D-register pairs.

This fixes PR12389.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153603 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAlso verify after ExpandPostRAPseudos.
Jakob Stoklund Olesen [Wed, 28 Mar 2012 20:49:30 +0000 (20:49 +0000)]
Also verify after ExpandPostRAPseudos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153599 91177308-0d34-0410-b5e6-96231b3b80d8