oota-llvm.git
9 years agoDeleting empty directories left over from r223794.
Frederic Riss [Tue, 9 Dec 2014 17:50:27 +0000 (17:50 +0000)]
Deleting empty directories left over from r223794.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223798 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[CGP] Rewrite pattern match for splitBranchCondition to work with Values instead.
Juergen Ributzka [Tue, 9 Dec 2014 17:50:10 +0000 (17:50 +0000)]
[CGP] Rewrite pattern match for splitBranchCondition to work with Values instead.

Rewrite the pattern match code to work also with Values instead with
Instructions only. Also remove the no longer need matcher (m_Instruction).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223797 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert "Move function to obtain branch weights into the BranchInst class. NFC."
Juergen Ributzka [Tue, 9 Dec 2014 17:32:12 +0000 (17:32 +0000)]
Revert "Move function to obtain branch weights into the BranchInst class. NFC."

This reverts commit r223784 and copies the 'ExtractBranchMetadata' to CodeGenPrepare.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223795 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert "Initial dsymutil tool commit."
Frederic Riss [Tue, 9 Dec 2014 17:21:50 +0000 (17:21 +0000)]
Revert "Initial dsymutil tool commit."

This reverts commit r223793. The review thread wasn't concluded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223794 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoInitial dsymutil tool commit.
Frederic Riss [Tue, 9 Dec 2014 17:03:30 +0000 (17:03 +0000)]
Initial dsymutil tool commit.

The goal of this tool is to replicate Darwin's dsymutil functionality
based on LLVM. dsymutil is a DWARF linker. Darwin's linker (ld64) does
not link the debug information, it leaves it in the object files in
relocatable form, but embbeds a `debug map` into the executable that
describes where to find the debug information and how to relocate it.
When releasing/archiving a binary, dsymutil is called to link all the DWARF
information into a `dsym bundle` that can distributed/stored along with
the binary.

With this commit, the LLVM based dsymutil is just able to parse the STABS
debug maps embedded by ld64 in linked binaries (and not all of them, for
example archives aren't supported yet).

Note that the tool directory is called dsymutil, but the executable is
currently called llvm-dsymutil. This discrepancy will disappear once the
tool will be feature complete. At this point the executable will be renamed
to dsymutil, but until then you do not want it to override the system one.

    Differential Revision: http://reviews.llvm.org/D6242

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223793 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC 4/4] Enable little-endian support for VSX.
Bill Schmidt [Tue, 9 Dec 2014 16:59:57 +0000 (16:59 +0000)]
[PowerPC 4/4] Enable little-endian support for VSX.

With the foregoing three patches, VSX instructions can be used for
little endian.  This patch removes the restriction that prevented
this, and re-enables the test cases from the first three patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223792 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC 3/4] Little-endian adjustments for VSX vector shuffle
Bill Schmidt [Tue, 9 Dec 2014 16:52:29 +0000 (16:52 +0000)]
[PowerPC 3/4] Little-endian adjustments for VSX vector shuffle

When performing instruction selection for ISD::VECTOR_SHUFFLE, there
is special code for handling v2f64 and v2i64 using VSX instructions.
This code must be adjusted for little-endian.  Because the two inputs
are treated as a double-wide register, we must swap their order for
little endian.  To get the appropriate mask elements to use with the
big-endian biased XXPERMDI instruction, we must reverse their order
and invert the bits.

A new test is added to test the 16 possible values of the shuffle
mask.  It is initially disabled for reasons specified in the test.  It
is re-enabled by patch 4/4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223791 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemember the unmangled name in the plugin.
Rafael Espindola [Tue, 9 Dec 2014 16:50:57 +0000 (16:50 +0000)]
Remember the unmangled name in the plugin.

This allows it to work with non trivial manglings like the one in COFF.

Amusingly, this can be tested with gold, as emit-llvm causes the plugin to
exit before any COFF is generated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223790 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd test cases that were inadvertently omitted from r223783 and r223788
Bill Schmidt [Tue, 9 Dec 2014 16:44:58 +0000 (16:44 +0000)]
Add test cases that were inadvertently omitted from r223783 and r223788

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223789 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC 2/4] Little-endian adjustments for VSX insert/extract operations
Bill Schmidt [Tue, 9 Dec 2014 16:43:32 +0000 (16:43 +0000)]
[PowerPC 2/4] Little-endian adjustments for VSX insert/extract operations

For little endian, we need to make some straightforward adjustments in
the code expansions for scalar_to_vector and vector_extract of v2f64.
First, scalar_to_vector must place the scalar into vector element
zero.  However, our implementation of SUBREG_TO_REG will place it into
big-element vector element zero (high-order bits), and for little
endian we need it in the low-order bits.  The LE implementation splats
the high-order doubleword into the low-order doubleword.

Second, the meaning of (vector_extract x, 0) and (vector_extract x, 1)
must be reversed for similar reasons.

A new test is added that tests code generation for insertelement and
extractelement for both element 0 and element 1.  It is disabled in
this patch but enabled in patch 4/4, for reasons stated in the test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223788 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[AVX512] Added VPBROADCAST{BWDQ} (Load with Broadcast Integer Data from General Purpo...
Robert Khasanov [Tue, 9 Dec 2014 16:38:41 +0000 (16:38 +0000)]
[AVX512] Added VPBROADCAST{BWDQ} (Load with Broadcast Integer Data from General Purpose Register) encodings for AVX512-BW/VL subsets
Added encoding tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223787 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[CodeGenPrepare] Split branch conditions into multiple conditional branches.
Juergen Ributzka [Tue, 9 Dec 2014 16:36:13 +0000 (16:36 +0000)]
[CodeGenPrepare] Split branch conditions into multiple conditional branches.

This optimization transforms code like:
bb1:
  %0 = icmp ne i32 %a, 0
  %1 = icmp ne i32 %b, 0
  %or.cond = or i1 %0, %1
  br i1 %or.cond, label %TrueBB, label %FalseBB

into a multiple branch instructions like:

bb1:
  %0 = icmp ne i32 %a, 0
  br i1 %0, label %TrueBB, label %bb2
bb2:
  %1 = icmp ne i32 %b, 0
  br i1 %1, label %TrueBB, label %FalseBB

This optimization is already performed by SelectionDAG, but not by FastISel.
FastISel cannot perform this optimization, because it cannot generate new
MachineBasicBlocks.

Performing this optimization at CodeGenPrepare time makes it available to both -
SelectionDAG and FastISel - and the implementation in SelectiuonDAG could be
removed. There are currenty a few differences in codegen for X86 and PPC, so
this commmit only enables it for FastISel.

Reviewed by Jim Grosbach

This fixes rdar://problem/19034919.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223786 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd more pattern matchers for compares, instructions, and BinaryOperators. NFC.
Juergen Ributzka [Tue, 9 Dec 2014 16:36:10 +0000 (16:36 +0000)]
Add more pattern matchers for compares, instructions, and BinaryOperators. NFC.

Add a few more matchers to make the code in the next commit more compact.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223785 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMove function to obtain branch weights into the BranchInst class. NFC.
Juergen Ributzka [Tue, 9 Dec 2014 16:36:06 +0000 (16:36 +0000)]
Move function to obtain branch weights into the BranchInst class. NFC.

Make this function available to other parts of LLVM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223784 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC 1/4] Little-endian adjustments for VSX loads/stores
Bill Schmidt [Tue, 9 Dec 2014 16:35:51 +0000 (16:35 +0000)]
[PowerPC 1/4] Little-endian adjustments for VSX loads/stores

This patch addresses the inherent big-endian bias in the lxvd2x,
lxvw4x, stxvd2x, and stxvw4x instructions.  These instructions load
vector elements into registers left-to-right (with the first element
loaded into the high-order bits of the register), regardless of the
endian setting of the processor.  However, these are the only
vector memory instructions that permit unaligned storage accesses, so
we want to use them for little-endian.

To make this work, a lxvd2x or lxvw4x is replaced with an lxvd2x
followed by an xxswapd, which swaps the doublewords.  This works for
lxvw4x as well as lxvd2x, because for lxvw4x on an LE system the
vector elements are in LE order (right-to-left) within each
doubleword.  (Thus after lxvw2x of a <4 x float> the elements will
appear as 1, 0, 3, 2.  Following the swap, they will appear as 3, 2,
0, 1, as desired.)   For stores, an stxvd2x or stxvw4x is replaced
with an stxvd2x preceded by an xxswapd.

Introduction of extra swap instructions provides correctness, but
obviously is not ideal from a performance perspective.  Future patches
will address this with optimizations to remove most of the introduced
swaps, which have proven effective in other implementations.

The introduction of the swaps is performed during lowering of LOAD,
STORE, INTRINSIC_W_CHAIN, and INTRINSIC_VOID operations.  The latter
are used to translate intrinsics that specify the VSX loads and stores
directly into equivalent sequences for little endian.  Thus code that
uses vec_vsx_ld and vec_vsx_st does not have to be modified to be
ported from BE to LE.

We introduce new PPCISD opcodes for LXVD2X, STXVD2X, and XXSWAPD for
use during this lowering step.  In PPCInstrVSX.td, we add new SDType
and SDNode definitions for these (PPClxvd2x, PPCstxvd2x, PPCxxswapd).
These are recognized during instruction selection and mapped to the
correct instructions.

Several tests that were written to use -mcpu=pwr7 or pwr8 are modified
to disable VSX on LE variants because code generation changes with
this and subsequent patches in this set.  I chose to include all of
these in the first patch than try to rigorously sort out which tests
were broken by one or another of the patches.  Sorry about that.

The new test vsx-ldst-builtin-le.ll, and the changes to vsx-ldst.ll,
are disabled until LE support is enabled because of breakages that
occur as noted in those tests.  They are re-enabled in patch 4/4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223783 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMove method out of line to make buildbot happy.
Rafael Espindola [Tue, 9 Dec 2014 16:18:11 +0000 (16:18 +0000)]
Move method out of line to make buildbot happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223781 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDon't lookup an object symbol name in the module.
Rafael Espindola [Tue, 9 Dec 2014 16:13:59 +0000 (16:13 +0000)]
Don't lookup an object symbol name in the module.

Instead, walk the obj symbol list in parallel to find the GV. This shouldn't
change anything on ELF where global symbols are not mangled, but it is a step
toward supporting other object formats.

Gold itself is ELF only, but bfd ld supports COFF and the logic in the gold
plugin could be reused on lld.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223780 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[x86] Fix the test to actually test things for the CPU names, add the
Chandler Carruth [Tue, 9 Dec 2014 14:25:55 +0000 (14:25 +0000)]
[x86] Fix the test to actually test things for the CPU names, add the
missing barcelona CPU which that test uncovered, and remove the 32-bit
x86 CPUs which I really wasn't prepared to audit and test thoroughly.

If anyone wants to clean up the 32-bit only x86 CPUs, go for it.

Also, if anyone else wants to try to de-duplicate the AMD CPUs, that'd
be cool, but from the looks of it wouldn't save as much as it did for
the Intel CPUs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223774 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemoving an unused variable to silence a -Wunused-but-set-variable warning. NFC.
Aaron Ballman [Tue, 9 Dec 2014 13:20:11 +0000 (13:20 +0000)]
Removing an unused variable to silence a -Wunused-but-set-variable warning. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223773 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix modified immediate bug reported by MC Hammer.
Asiri Rathnayake [Tue, 9 Dec 2014 13:14:58 +0000 (13:14 +0000)]
Fix modified immediate bug reported by MC Hammer.

Instructions of the form [ADD Rd, pc, #imm] are manually aliased
in processInstruction() to use ADR. To accomodate this, mod_imm handling
had to be tweaked a bit. Turns out it was the manual aliasing that must
be tweaked to accommodate mod_imms instead. More information about the
parsed instruction is available at the point where processInstruction()
is invoked, which makes it easier to detect a mod_imm at that point rather
than trying to detect a potential alias when a mod_imm is being prepped.
Added a test case and fixed some white spaces as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223772 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[x86] Add a test for the CPU names that should have been in r223769.
Chandler Carruth [Tue, 9 Dec 2014 11:19:57 +0000 (11:19 +0000)]
[x86] Add a test for the CPU names that should have been in r223769.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223770 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[x86] Bring some sanity to the x86 CPU processor definitions.
Chandler Carruth [Tue, 9 Dec 2014 10:58:36 +0000 (10:58 +0000)]
[x86] Bring some sanity to the x86 CPU processor definitions.

Notably, this adds simple micro-architecture names for the Intel CPU
variants, and defines the old 'core'-based names as aliases. GCC has
started to simplify their documented interface to use these names as
well, so it seems like we can start to converge on a consistent pattern.

I'd appreciate Intel double checking the entries that aren't yet
documented widely, especially Atom (Bonnell and Silvermont), Knights
Landing, and Skylake. But this change shouldn't break any existing
users.

Also, ran clang-format to re-format this code and it actually worked
(modulo a tiny bug) so hopefully we can start to stop thinking about
formatting this stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223769 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemoval Of Duplicate Test Cases and Addition Of Missing Check Statements
Sonam Kumari [Tue, 9 Dec 2014 10:46:38 +0000 (10:46 +0000)]
Removal Of Duplicate Test Cases and Addition Of Missing Check Statements

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223768 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[test/Transforms/InstCombine/shift.ll] Removed duplicate test cases. NFC.
Ankur Garg [Tue, 9 Dec 2014 10:35:19 +0000 (10:35 +0000)]
[test/Transforms/InstCombine/shift.ll] Removed duplicate test cases. NFC.

Removed some duplicate test cases from the file /test/Transforms/InstCombine/shift.ll.

test54 and test57 were duplicates of each other.
test55 and test58 were duplicates of each other.

(Removed test57 and test58)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223767 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoImprove emacs coding style
Will Newton [Tue, 9 Dec 2014 08:58:31 +0000 (08:58 +0000)]
Improve emacs coding style

Remove setting of default style, this way is not recommended and
means that all the settings have to be duplicated to demonstrate the
c-add-style method which is a much better way of doing it.

Remove the modified date as it is better stored in SVN.

Tweak a few style parameters to make them conform to the actual LLVM
style.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223765 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTeach instcombine to canonicalize "element extraction" from a load of an
Chandler Carruth [Tue, 9 Dec 2014 08:55:32 +0000 (08:55 +0000)]
Teach instcombine to canonicalize "element extraction" from a load of an
integer and "element insertion" into a store of an integer into actual
element extraction, element insertion, and vector loads and stores.

Previously various parts of LLVM (including instcombine itself) would
introduce integer loads and stores into the code as a way of opaquely
loading and storing "bits". In some cases (such as a memcpy of
std::complex<float> object) we will eventually end up using those bits
in non-integer types. In order for SROA to effectively promote the
allocas involved, it splits these "store a bag of bits" integer loads
and stores up into the constituent parts. However, for non-alloca loads
and tsores which remain, it uses integer math to recombine the values
into a large integer to load or store.

All of this would be "fine", except that it forces LLVM to go through
integer math to combine and split up values. While this makes perfect
sense for integers (and in fact is critical for bitfields to end up
lowering efficiently) it is *terrible* for non-integer types, especially
floating point types. We have a much more canonical way of representing
the act of concatenating the bits of two SSA values in LLVM: a vector
and insertelement. This patch teaching InstCombine to use this
representation.

With this patch applied, LLVM will no longer introduce integer math into
the critical path of every loop over std::complex<float> operations such
as those that make up the hot path of ... oh, most HPC code, Eigen, and
any other heavy linear algebra library.

For the record, I looked *extensively* at fixing this in other parts of
the compiler, but it just doesn't work:
- We really do want to canonicalize memcpy and other bit-motion to
  integer loads and stores. SSA values are tremendously more powerful
  than "copy" intrinsics. Not doing this regresses massive amounts of
  LLVM's scalar optimizer.
- We really do need to split up integer loads and stores of this form in
  SROA or every memcpy of a trivially copyable struct will prevent SSA
  formation of the members of that struct. It essentially turns off
  SROA.
- The closest alternative is to actually split the loads and stores when
  partitioning with SROA, but this has all of the downsides historically
  discussed of splitting up loads and stores -- the wide-store
  information is fundamentally lost. We would also see performance
  regressions for bitfield-heavy code and other places where the
  integers aren't really intended to be split without seemingly
  arbitrary logic to treat integers totally differently.
- We *can* effectively fix this in instcombine, so it isn't that hard of
  a choice to make IMO.

Differential Revision: http://reviews.llvm.org/D6548

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223764 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSkip declarations in the case of functions.
Michael Ilseman [Tue, 9 Dec 2014 08:20:06 +0000 (08:20 +0000)]
Skip declarations in the case of functions.

This is a revert of r223521 in spirit, if not in content. I am not
sure why declarations ended up in LazilyLinkGlobalValues in the first
place; that will take some more investigation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223763 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse range-based for loops. NFC.
Craig Topper [Tue, 9 Dec 2014 08:05:51 +0000 (08:05 +0000)]
Use range-based for loops. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223762 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAVX-512: Added some comments to ERI scalar intrinsics.
Elena Demikhovsky [Tue, 9 Dec 2014 07:06:32 +0000 (07:06 +0000)]
AVX-512: Added some comments to ERI scalar intrinsics.
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223761 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix a few instances found in SelectionDAG where we were not handling F16 at parity...
Owen Anderson [Tue, 9 Dec 2014 06:50:39 +0000 (06:50 +0000)]
Fix a few instances found in SelectionDAG where we were not handling F16 at parity with F32 and F64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223760 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agotest commit (spelling correction)
Mohit K. Bhakkad [Tue, 9 Dec 2014 06:31:07 +0000 (06:31 +0000)]
test commit (spelling correction)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223758 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Convert esp-relative movs of function arguments into pushes, step 1
Michael Kuperstein [Tue, 9 Dec 2014 06:10:44 +0000 (06:10 +0000)]
[X86] Convert esp-relative movs of function arguments into pushes, step 1

This handles the simplest case for mov -> push conversion:
1. x86-32 calling convention, everything is passed through the stack.
2. There is no reserved call frame.
3. Only registers or immediates are pushed, no attempt to combine a mem-reg-mem sequence into a single PUSHmm.

Differential Revision: http://reviews.llvm.org/D6503

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223757 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoReland r223754
David Majnemer [Tue, 9 Dec 2014 05:56:09 +0000 (05:56 +0000)]
Reland r223754

The commit is identical except a reference to `GV' should have been to
`GVal'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223756 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert "AsmParser: Reject invalid mismatch between forward ref and def"
David Majnemer [Tue, 9 Dec 2014 05:50:11 +0000 (05:50 +0000)]
Revert "AsmParser: Reject invalid mismatch between forward ref and def"

This reverts commit r223754.  I've upset the buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223755 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAsmParser: Reject invalid mismatch between forward ref and def
David Majnemer [Tue, 9 Dec 2014 05:43:56 +0000 (05:43 +0000)]
AsmParser: Reject invalid mismatch between forward ref and def

Don't assume that the forward referenced entity was of the same
global-kind as the new entity.

This fixes PR21779.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223754 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRestore r223709 as it was meant to be, and enable FeatureP8Vector for P8
Bill Schmidt [Tue, 9 Dec 2014 03:02:48 +0000 (03:02 +0000)]
Restore r223709 as it was meant to be, and enable FeatureP8Vector for P8

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223751 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert r223709, "[PowerPC]Activate FeatureVSX for the Power target", to unbreak bots.
NAKAMURA Takumi [Tue, 9 Dec 2014 01:03:27 +0000 (01:03 +0000)]
Revert r223709, "[PowerPC]Activate FeatureVSX for the Power target", to unbreak bots.

CodeGen/PowerPC/vsx-p8.ll was failing.

  '+power8-vector' is not a recognized feature for this target (ignoring feature)
  llvm/test/CodeGen/PowerPC/vsx-p8.ll:33:14: error: expected string not found in input
  ; CHECK-REG: lxvw4x 34, 0, 3
               ^
  <stdin>:50:2: note: scanning from here
   .align 3
   ^
  <stdin>:61:2: note: possible intended match here
   lvx 3, 0, 3
   ^

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223729 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoHandle early-clobber registers in the aggressive anti-dep breaker
Hal Finkel [Tue, 9 Dec 2014 01:00:59 +0000 (01:00 +0000)]
Handle early-clobber registers in the aggressive anti-dep breaker

The aggressive anti-dep breaker, used by the PowerPC backend during post-RA
scheduling (but is available to all targets), did not handle early-clobber MI
operands (at all). When constructing the list of available registers for the
replacement of some def operand, check the using instructions, and remove
registers assigned to early-clobbered defs from the set.

Fixes PR21452.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223727 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd argument variable support to the debug info tutorial
Eric Christopher [Tue, 9 Dec 2014 00:28:24 +0000 (00:28 +0000)]
Add argument variable support to the debug info tutorial
and rearrange the prologue source location hack to immediately
after it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223725 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Set MayStore = 0 on MUBUF loads
Tom Stellard [Tue, 9 Dec 2014 00:03:54 +0000 (00:03 +0000)]
R600/SI: Set MayStore = 0 on MUBUF loads

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223722 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Move setting of the lds bit to the base MUBUF class
Tom Stellard [Tue, 9 Dec 2014 00:03:51 +0000 (00:03 +0000)]
R600/SI: Move setting of the lds bit to the base MUBUF class

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223721 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Removing old def versions and replacing usages with versions that have...
Colin LeMahieu [Mon, 8 Dec 2014 23:55:43 +0000 (23:55 +0000)]
[Hexagon] Removing old def versions and replacing usages with versions that have encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223720 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMISched: Fix moving stores across barriers
Tom Stellard [Mon, 8 Dec 2014 23:36:48 +0000 (23:36 +0000)]
MISched: Fix moving stores across barriers

This fixes an issue with ScheduleDAGInstrs::buildSchedGraph
where stores without an underlying object would not be added
as a predecessor to the current BarrierChain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223717 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding any8, all8, and/or/xor/andn/orn/not predicate register forms, mask...
Colin LeMahieu [Mon, 8 Dec 2014 23:07:59 +0000 (23:07 +0000)]
[Hexagon] Adding any8, all8, and/or/xor/andn/orn/not predicate register forms, mask, and vitpack instructions and patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223710 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC]Activate FeatureVSX for the Power target
Bill Seurer [Mon, 8 Dec 2014 23:07:12 +0000 (23:07 +0000)]
[PowerPC]Activate FeatureVSX for the Power target

This change activates FeatureVSX for Power 7 and Power 8 in PPC.td.

http://reviews.llvm.org/D6570

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223709 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Don't use a non-allocatable register to implement the 'cc' alias
Hal Finkel [Mon, 8 Dec 2014 22:54:22 +0000 (22:54 +0000)]
[PowerPC] Don't use a non-allocatable register to implement the 'cc' alias

GCC accepts 'cc' as an alias for 'cr0', and we need to do the same when
processing inline asm constraints. This had previously been implemented using a
non-allocatable register, named 'cc', that was listed as an alias of 'cr0', but
the infrastructure does not seem to support this properly (neither the register
allocator nor the scheduler properly accounts for the alias). Instead, we can
just process this as a naming alias inside of the inline asm
constraint-processing code, so we'll do that instead.

There are two regression tests, one where the post-RA scheduler did the wrong
thing with the non-allocatable alias, and one where the register allocator did
the wrong thing. Fixes PR21742.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223708 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Fixing broken test.
Colin LeMahieu [Mon, 8 Dec 2014 22:29:06 +0000 (22:29 +0000)]
[Hexagon] Fixing broken test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223704 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding xtype doubleword add, sub, and, or, xor and patterns.
Colin LeMahieu [Mon, 8 Dec 2014 22:19:14 +0000 (22:19 +0000)]
[Hexagon] Adding xtype doubleword add, sub, and, or, xor and patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223702 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding xtype doubleword comparisons. Removing unused multiclass.
Colin LeMahieu [Mon, 8 Dec 2014 21:56:47 +0000 (21:56 +0000)]
[Hexagon] Adding xtype doubleword comparisons.  Removing unused multiclass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223701 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding xtype parity, min, minu, max, maxu instructions.
Colin LeMahieu [Mon, 8 Dec 2014 21:19:18 +0000 (21:19 +0000)]
[Hexagon] Adding xtype parity, min, minu, max, maxu instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223693 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh/sat/<<16 instructions.
Colin LeMahieu [Mon, 8 Dec 2014 20:33:01 +0000 (20:33 +0000)]
[Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh/sat/<<16 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223692 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMake myself the code owner for llgo.
Peter Collingbourne [Mon, 8 Dec 2014 20:30:39 +0000 (20:30 +0000)]
Make myself the code owner for llgo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223691 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Move continue after checking s_mov_b32.
Matt Arsenault [Mon, 8 Dec 2014 19:55:43 +0000 (19:55 +0000)]
R600/SI: Move continue after checking s_mov_b32.

There's nothing else to bother trying to shrink these.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223686 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoConstantFold: Zero-sized globals might land on top of another global
David Majnemer [Mon, 8 Dec 2014 19:35:31 +0000 (19:35 +0000)]
ConstantFold: Zero-sized globals might land on top of another global

A zero sized array is zero sized and might share its address with
another global.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223684 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoClean up the rst for the debug info tutorial
Eric Christopher [Mon, 8 Dec 2014 18:48:08 +0000 (18:48 +0000)]
Clean up the rst for the debug info tutorial

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223682 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoLazily link GlobalVariables and GlobalAliases.
Rafael Espindola [Mon, 8 Dec 2014 18:45:16 +0000 (18:45 +0000)]
Lazily link GlobalVariables and GlobalAliases.

We were already lazily linking functions, but all GlobalValues can be treated
uniformly for this.

The test updates are to ensure that a given GlobalValue is still linked in.

This fixes pr21494.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223681 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding add/sub with saturation. Removing unused def. Cleaning up shift...
Colin LeMahieu [Mon, 8 Dec 2014 18:33:49 +0000 (18:33 +0000)]
[Hexagon] Adding add/sub with saturation.  Removing unused def.  Cleaning up shift patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223680 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoInstSimplify: Try to bring back the rest of r223583
David Majnemer [Mon, 8 Dec 2014 18:30:43 +0000 (18:30 +0000)]
InstSimplify: Try to bring back the rest of r223583

This reverts r223624 with a small tweak, hopefully this will make stage3
equivalent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223679 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoOnce more on the cmake build. nativecodegen->native on the dependencies.
Eric Christopher [Mon, 8 Dec 2014 18:24:06 +0000 (18:24 +0000)]
Once more on the cmake build. nativecodegen->native on the dependencies.

Thanks to Rafael Espindola for testing assistance.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223678 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAttempt to fix the cmake build by requiring mcjit on the cmake
Eric Christopher [Mon, 8 Dec 2014 18:20:50 +0000 (18:20 +0000)]
Attempt to fix the cmake build by requiring mcjit on the cmake
dependencies for the KS tutorials

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223677 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[CompactUnwind] Fix register encoding logic
Bruno Cardoso Lopes [Mon, 8 Dec 2014 18:18:32 +0000 (18:18 +0000)]
[CompactUnwind] Fix register encoding logic

Fix a compact unwind encoding logic bug which would try to encode
more callee saved registers than it should, leading to early bail out
in the encoding logic and abusive use of DWARF frame mode unnecessarily.

Also remove no-compact-unwind.ll which was testing the wrong thing
based on this bug and move it to valid 'compact unwind' tests. Added
other few more tests too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223676 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix KS tutorial build failure.
Eric Christopher [Mon, 8 Dec 2014 18:12:28 +0000 (18:12 +0000)]
Fix KS tutorial build failure.

make all doesn't build the examples and it was uniquified since
last build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223675 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDon't crash when the key of a comdat is lazily linked.
Rafael Espindola [Mon, 8 Dec 2014 18:05:48 +0000 (18:05 +0000)]
Don't crash when the key of a comdat is lazily linked.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223673 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoInstrProf: An intrinsic and lowering for instrumentation based profiling
Justin Bogner [Mon, 8 Dec 2014 18:02:35 +0000 (18:02 +0000)]
InstrProf: An intrinsic and lowering for instrumentation based profiling

Introduce the ``llvm.instrprof_increment`` intrinsic and the
``-instrprof`` pass. These provide the infrastructure for writing
counters for profiling, as in clang's ``-fprofile-instr-generate``.

The implementation of the instrprof pass is ported directly out of the
CodeGenPGO classes in clang, and with the followup in clang that rips
that code out to use these new intrinsics this ends up being NFC.

Doing the instrumentation this way opens some doors in terms of
improving the counter performance. For example, this will make it
simple to experiment with alternate lowering strategies, and allows us
to try handling profiling specially in some optimizations if we want
to.

Finally, this drastically simplifies the frontend and puts all of the
lowering logic in one place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223672 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd Chapter 8 to the Kaleidoscope tutorial. This chapter adds
Eric Christopher [Mon, 8 Dec 2014 18:00:47 +0000 (18:00 +0000)]
Add Chapter 8 to the Kaleidoscope tutorial. This chapter adds
a description of how to add debug information using DWARF and
DIBuilder to the language.

Thanks to David Blaikie for his assistance with this tutorial.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223671 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix the JIT code for the Kaleidoscope tutorial.
Eric Christopher [Mon, 8 Dec 2014 18:00:38 +0000 (18:00 +0000)]
Fix the JIT code for the Kaleidoscope tutorial.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223670 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAArch64: treat HFAs containing "half" types as blocks too.
Tim Northover [Mon, 8 Dec 2014 17:54:58 +0000 (17:54 +0000)]
AArch64: treat HFAs containing "half" types as blocks too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223669 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Improved tablegen patters for matching TZCNT/LZCNT.
Andrea Di Biagio [Mon, 8 Dec 2014 17:47:18 +0000 (17:47 +0000)]
[X86] Improved tablegen patters for matching TZCNT/LZCNT.

Teach ISel how to match a TZCNT/LZCNT from a conditional move if the
condition code is X86_COND_NE.
Existing tablegen patterns only allowed to match TZCNT/LZCNT from a
X86cond with condition code equal to X86_COND_E. To avoid introducing
extra rules, I added an 'ImmLeaf' definition that checks if the
condition code is COND_E or COND_NE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223668 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding combine reg, reg with predicated forms.
Colin LeMahieu [Mon, 8 Dec 2014 17:33:06 +0000 (17:33 +0000)]
[Hexagon] Adding combine reg, reg with predicated forms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223667 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSimplify the test. NFC.
Rafael Espindola [Mon, 8 Dec 2014 17:22:06 +0000 (17:22 +0000)]
Simplify the test. NFC.

Since the main file was empty, we can just copy the content of the Input file
into it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223666 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSimplify test. NFC.
Rafael Espindola [Mon, 8 Dec 2014 17:02:50 +0000 (17:02 +0000)]
Simplify test. NFC.

This is just testing the largest merge mode for comdats. No need to use
hard to read names and fancy types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223665 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding packhl instruction.
Colin LeMahieu [Mon, 8 Dec 2014 17:01:18 +0000 (17:01 +0000)]
[Hexagon] Adding packhl instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223664 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse CHECK-DAG to reduce the noise in an upcoming patch.
Rafael Espindola [Mon, 8 Dec 2014 16:46:52 +0000 (16:46 +0000)]
Use CHECK-DAG to reduce the noise in an upcoming patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223663 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] Add Mips-specific CCIf's for accessing the MipsCCState. NFC.
Daniel Sanders [Mon, 8 Dec 2014 15:40:09 +0000 (15:40 +0000)]
[mips] Add Mips-specific CCIf's for accessing the MipsCCState. NFC.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6213

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223662 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Improved lowering of packed v8i16 vector shifts by non-constant count.
Andrea Di Biagio [Mon, 8 Dec 2014 14:36:51 +0000 (14:36 +0000)]
[X86] Improved lowering of packed v8i16 vector shifts by non-constant count.

Before this patch, the backend sub-optimally expanded the non-constant shift
count of a v8i16 shift into a sequence of two 'movd' plus 'movzwl'.

With this patch the backend checks if the target features sse4.1. If so, then
it lets the shuffle legalizer deal with the expansion of the shift amount.

Example:
;;
define <8 x i16> @test(<8 x i16> %A, <8 x i16> %B) {
  %shamt = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
  %shl = shl <8 x i16> %A, %shamt
  ret <8 x i16> %shl
}
;;

Before (with -mattr=+avx):
  vmovd  %xmm1, %eax
  movzwl  %ax, %eax
  vmovd  %eax, %xmm1
  vpsllw  %xmm1, %xmm0, %xmm0
  retq

Now:
  vpxor  %xmm2, %xmm2, %xmm2
  vpblendw  $1, %xmm1, %xmm2, %xmm1
  vpsllw  %xmm1, %xmm0, %xmm0
  retq

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223660 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMove the ValueMap lookup inside linkFunctionBody. NFC.
Rafael Espindola [Mon, 8 Dec 2014 14:25:26 +0000 (14:25 +0000)]
Move the ValueMap lookup inside linkFunctionBody. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223659 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse range loops. NFC.
Rafael Espindola [Mon, 8 Dec 2014 14:20:10 +0000 (14:20 +0000)]
Use range loops. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223658 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse range loops. NFC.
Rafael Espindola [Mon, 8 Dec 2014 14:05:33 +0000 (14:05 +0000)]
Use range loops. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223657 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix linking of prologue data.
Rafael Espindola [Mon, 8 Dec 2014 13:44:38 +0000 (13:44 +0000)]
Fix linking of prologue data.

It would crash when the function was lazy linked.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223656 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[CMake] Fix installation of llvm-ranlib on multiconfig builder.
NAKAMURA Takumi [Mon, 8 Dec 2014 13:43:38 +0000 (13:43 +0000)]
[CMake] Fix installation of llvm-ranlib on multiconfig builder.

Introduce install_symlink.cmake from clang/tools/driver/clang_symlink.cmake.

FIXME: Would it be generalized?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223655 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSimple style fixes.
Rafael Espindola [Mon, 8 Dec 2014 13:35:09 +0000 (13:35 +0000)]
Simple style fixes.

* Use a range loop.
* Move simple continue checks earlier.
* clang-format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223654 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMove materialize/Dematerialize calls to linkFunctionBody. NFC.
Rafael Espindola [Mon, 8 Dec 2014 13:29:33 +0000 (13:29 +0000)]
Move materialize/Dematerialize calls to linkFunctionBody. NFC.

Just less code duplication.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223653 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemoval Of Duplicate Test Case from shift.ll file
Sonam Kumari [Mon, 8 Dec 2014 09:40:43 +0000 (09:40 +0000)]
Removal Of Duplicate Test Case from shift.ll file

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223648 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoX86 intrinsics moved form X86ISelLowering.cpp to X86IntrinsicsInfo.h
Elena Demikhovsky [Mon, 8 Dec 2014 09:03:08 +0000 (09:03 +0000)]
X86 intrinsics moved form X86ISelLowering.cpp to X86IntrinsicsInfo.h
X86ISelLowering.cpp has a long switch for intrinsics. I moved a part of
this long switch to the new intrinsics table in X86IntrinsicsInfo.h.
No functional changes, just code and compile time optimization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223641 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agolit: Don't use python 2.6 features
David Majnemer [Mon, 8 Dec 2014 08:33:30 +0000 (08:33 +0000)]
lit: Don't use python 2.6 features

LLVM supports python 2.5, this fixes a (somewhat) recent regression.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223626 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert a part of r223583, for now. It seems causing different emission between stage2...
NAKAMURA Takumi [Mon, 8 Dec 2014 02:07:22 +0000 (02:07 +0000)]
Revert a part of r223583, for now. It seems causing different emission between stage2(gcc-clang) and stage3 clang. Investigating.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223624 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoIR: Fix bitcode compatability filenames
Duncan P. N. Exon Smith [Mon, 8 Dec 2014 00:41:39 +0000 (00:41 +0000)]
IR: Fix bitcode compatability filenames

As a fixup to r223616, follow the convention of naming the files after
the LLVM release whose bitcode they're maintaining compatability with.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223623 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoIR: Revert r223618 behaviour of MDNode::concatenate()
Duncan P. N. Exon Smith [Sun, 7 Dec 2014 20:32:11 +0000 (20:32 +0000)]
IR: Revert r223618 behaviour of MDNode::concatenate()

r223618 including special handling of `MDNode::intersect()`: if the
first operand is a self-reference with the same operands you're trying
to return, return it instead.

Reuse that handling in `MDNode::concatenate()` in the hopes that it
fixes a polly test that seems to rely on the old behaviour [1].

[1]: http://lab.llvm.org:8011/builders/polly-amd64-linux/builds/25167

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223619 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoIR: Drop uniquing for self-referencing MDNodes
Duncan P. N. Exon Smith [Sun, 7 Dec 2014 19:52:06 +0000 (19:52 +0000)]
IR: Drop uniquing for self-referencing MDNodes

It doesn't make sense to unique self-referencing nodes.  Drop uniquing
for them.

Note that `MDNode::intersect()` occasionally returns self-referencing
nodes.  Previously these would be returned by `MDNode::get()`.  I'm not
convinced this was intended behaviour -- to me it seems it should return
a node whose only operand is the self-reference -- but I don't know much
about alias scopes so I'm preserving it for now.

This is part of PR21532.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223618 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoIR: Remove reference to ENABLE_MDNODE_UNIQUING
Duncan P. N. Exon Smith [Sun, 7 Dec 2014 19:02:48 +0000 (19:02 +0000)]
IR: Remove reference to ENABLE_MDNODE_UNIQUING

Apparently `MDNode` uniquing used to be optional.  I suppose the
configure flag must have disappeared at some point.  Change the test so
it actually tests uniquing, and remove the check for
`ENABLE_MDNODE_UNIQUING`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223617 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoIR: Add missing tests for function-local metadata
Duncan P. N. Exon Smith [Sun, 7 Dec 2014 17:56:16 +0000 (17:56 +0000)]
IR: Add missing tests for function-local metadata

Add assembly and bitcode tests that I neglected to add in r223564 (IR:
Disallow complicated function-local metadata) and r223574 (IR: Disallow
function-local metadata attachments).

Found a couple of bugs:

  - The error message for function-local attachments gave the wrong line
    number -- it indicated the next token (typically on the next line)
    instead of the token that started the attachment.  Fixed.

  - Metadata arguments of the form `!{i32 0, i32 %v}` (or with the
    arguments reversed) fired an assertion in `ValueEnumerator` in LLVM
    v3.5, so I suppose this never really worked.  I suppose this was
    "fixed" by r223564.

(Thanks to dblaikie for pointing out my omission.)

Part of PR21532.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223616 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Disable VMEM and SMEM clauses by breaking them with S_NOP
Marek Olsak [Sun, 7 Dec 2014 17:17:43 +0000 (17:17 +0000)]
R600/SI: Disable VMEM and SMEM clauses by breaking them with S_NOP

This is only a workaround.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223615 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Set 20-bit immediate byte offset for SMRD on VI
Marek Olsak [Sun, 7 Dec 2014 17:17:38 +0000 (17:17 +0000)]
R600/SI: Set 20-bit immediate byte offset for SMRD on VI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223614 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[x86] Clean up the SSE1 test to use a slightly different pattern for
Chandler Carruth [Sun, 7 Dec 2014 17:16:00 +0000 (17:16 +0000)]
[x86] Clean up the SSE1 test to use a slightly different pattern for
matching offsets. I don't expect this to really matter, but its what the
latest incarnation of my script for maintaining these tests happens to
produce, and so its simpler for me if everything matches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223613 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[x86] Switch a constant selection test to use positive assertions and to
Chandler Carruth [Sun, 7 Dec 2014 17:15:58 +0000 (17:15 +0000)]
[x86] Switch a constant selection test to use positive assertions and to
store to real pointers so that its clear that the right code is in fact
being generated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223612 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[x86] Cleanup the combining vector shuffle tests a bit by merging
Chandler Carruth [Sun, 7 Dec 2014 17:15:56 +0000 (17:15 +0000)]
[x86] Cleanup the combining vector shuffle tests a bit by merging
identical checks for different SSE variants into a single block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223611 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[x86] Clean up the shift lowering vector shuffle tests a bit using my
Chandler Carruth [Sun, 7 Dec 2014 17:15:53 +0000 (17:15 +0000)]
[x86] Clean up the shift lowering vector shuffle tests a bit using my
script. Notably this folds all the SSE cases together into a single
FileCheck block. It also adds a vex prefix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223610 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Update instruction conversions for VI
Marek Olsak [Sun, 7 Dec 2014 12:19:03 +0000 (12:19 +0000)]
R600/SI: Update instruction conversions for VI

There are 3 changes:
- Convert 32-bit S_LSHL/LSHR/ASHR to their V_*REV variants for VI
- Lower RSQ_CLAMP for VI
- Don't generate MIN/MAX_LEGACY on VI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223604 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Add VI instructions
Marek Olsak [Sun, 7 Dec 2014 12:18:57 +0000 (12:18 +0000)]
R600/SI: Add VI instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223603 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Add SCC Defs/Uses to SOP1 and SOP2 opcodes
Marek Olsak [Sun, 7 Dec 2014 12:18:45 +0000 (12:18 +0000)]
R600/SI: Add SCC Defs/Uses to SOP1 and SOP2 opcodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223602 91177308-0d34-0410-b5e6-96231b3b80d8