From: John Criswell Date: Fri, 25 Jun 2004 15:16:57 +0000 (+0000) Subject: Added missing quote. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=fa0818711ae6f226cece78c1f79238bb683ef911;p=oota-llvm.git Added missing quote. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14407 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/docs/LangRef.html b/docs/LangRef.html index b71d3e1e1f2..729dcdf118f 100644 --- a/docs/LangRef.html +++ b/docs/LangRef.html @@ -764,7 +764,7 @@ match the return type of the function.

Semantics:

When the 'ret' instruction is executed, control flow returns back to the calling function's context. If the caller is a "call instruction, execution continues at + href="#i_call">call" instruction, execution continues at the instruction after the call. If the caller was an "invoke" instruction, execution continues at the beginning "normal" of the destination block. If the instruction @@ -2357,6 +2357,52 @@ ensures that accesses to memory mapped I/O registers occur in program order. + +

+ 'llvm.interrupt_handler' Intrinsic +
+ +
+ +
Syntax:
+
+  call void (void)* %llvm.interrupt_handler (void)
+
+ +
Overview:
+ +

+The 'llvm.interrupt_handler' intrinsic installs the specified function +as an interrupt handler for the specified interrupt. +

+ +
Arguments:
+ +

+The first argument is the value to write to the memory mapped I/O location. +The second argument is a pointer indicating the memory address to which the +data should be written. +

+ +
Semantics:
+ +

+The 'llvm.writeio' intrinsic writes value to the memory mapped +I/O address specified by pointer. The value must be a +first class type. However, certain architectures +may not support I/O on all first class types. For example, 32 bit processors +may only support I/O on data types that are 32 bits or less. +

+ +

+This intrinsic enforces an in-order memory model for llvm.readio and +llvm.writeio calls on machines that use dynamic scheduling. Dynamically +scheduled processors may execute loads and stores out of order, re-ordering at +run time accesses to memory mapped I/O registers. Using these intrinsics +ensures that accesses to memory mapped I/O registers occur in program order. +

+ +