From: Eric Christopher <echristo@apple.com>
Date: Fri, 20 Aug 2010 00:36:24 +0000 (+0000)
Subject: Fix loop conditionals (MO.isDef() asserts that it's a reg) and
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=f762fbe4fa421c91e20044ee009ddb57e25dd135;p=oota-llvm.git

Fix loop conditionals (MO.isDef() asserts that it's a reg) and
move some constraints around.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111594 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index a61fca1f252..6281c3a3b0b 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -122,7 +122,8 @@ bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
   // Look to see if our OptionalDef is defining CPSR or CCR.
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (MO.isDef() && MO.isReg() && MO.getReg() == ARM::CPSR)
+    if (!MO.isReg() || !MO.isDef()) continue;
+    if (MO.getReg() == ARM::CPSR)
       *CPSR = true;
   }
   return true;