From: Akira Hatanaka <ahatanaka@mips.com>
Date: Sat, 2 Jun 2012 00:02:45 +0000 (+0000)
Subject: Expand unaligned i16 loads/stores for the Mips backend.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=f66b7b1ff667bbcf9d71f540488b49b38bf72b1d;p=oota-llvm.git

Expand unaligned i16 loads/stores for the Mips backend.

This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157862 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 6ea2692d6f8..d0ea2185e0c 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -292,7 +292,6 @@ bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
   switch (SVT) {
   case MVT::i64:
   case MVT::i32:
-  case MVT::i16:
     return true;
   case MVT::f32:
     return Subtarget->hasMips32r2Or64();