From: Benjamin Kramer Date: Tue, 21 May 2013 08:51:09 +0000 (+0000) Subject: DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & 0) == 0. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=f19b8b018be4b0478f741bf35287db3488fda8d6;p=oota-llvm.git DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & 0) == 0. Fixes PR16083. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182357 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 36add035159..e8b6c04a48f 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1162,7 +1162,8 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, } // Make sure we're not losing bits from the constant. - if (MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) { + if (MinBits > 0 && + MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) { EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { // Will get folded away. diff --git a/test/CodeGen/X86/shrink-compare.ll b/test/CodeGen/X86/shrink-compare.ll index 0c16f86ff13..83793f000d5 100644 --- a/test/CodeGen/X86/shrink-compare.ll +++ b/test/CodeGen/X86/shrink-compare.ll @@ -50,3 +50,19 @@ if.end: ; CHECK: test3: ; CHECK: cmpb $-1, %{{dil|cl}} } + +; PR16083 +define i1 @test4(i64 %a, i32 %b) { +entry: + %tobool = icmp ne i32 %b, 0 + br i1 %tobool, label %lor.end, label %lor.rhs + +lor.rhs: ; preds = %entry + %and = and i64 0, %a + %tobool1 = icmp ne i64 %and, 0 + br label %lor.end + +lor.end: ; preds = %lor.rhs, %entry + %p = phi i1 [ true, %entry ], [ %tobool1, %lor.rhs ] + ret i1 %p +}