From: Jakob Stoklund Olesen <stoklund@2pi.dk>
Date: Fri, 29 Jul 2011 23:36:21 +0000 (+0000)
Subject: Don't check liveness of unallocatable registers.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=eeb57c7701ded683d660ed616966cfe7b1750337;p=oota-llvm.git

Don't check liveness of unallocatable registers.

This includes registers like EFLAGS and ST0-ST7. We don't check for
liveness issues in the verifier and scavenger because registers will
never be allocated from these classes.

While in SSA form, we do care about the liveness of unallocatable
unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for
MachineDCE and MachineSinking.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136541 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp
index 8541d18ef3e..f798c1346e0 100644
--- a/lib/CodeGen/MachineVerifier.cpp
+++ b/lib/CodeGen/MachineVerifier.cpp
@@ -664,8 +664,15 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
       // Use of a dead register.
       if (!regsLive.count(Reg)) {
         if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
-          // Reserved registers may be used even when 'dead'.
-          if (!isReserved(Reg))
+          // Reserved registers may be used even when 'dead', but allocatable
+          // registers can't.
+          // We track the liveness of unreserved, unallocatable registers while
+          // the machine function is still in SSA form. That lets us check for
+          // bad EFLAGS uses. After register allocation, the unallocatable
+          // registers are probably quite wrong. For example, the x87 ST0-ST7
+          // registers don't track liveness at all.
+          if (!isReserved(Reg) &&
+              (MRI->isSSA() || TRI->isInAllocatableClass(Reg)))
             report("Using an undefined physical register", MO, MONum);
         } else {
           BBInfo &MInfo = MBBInfoMap[MI->getParent()];
diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index 9e9a145b0aa..4fc711e1b8b 100644
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -157,7 +157,7 @@ void RegScavenger::forward() {
     if (!MO.isReg())
       continue;
     unsigned Reg = MO.getReg();
-    if (!Reg || isReserved(Reg))
+    if (!Reg || isReserved(Reg) || !TRI->isInAllocatableClass(Reg))
       continue;
 
     if (MO.isUse()) {
@@ -184,7 +184,7 @@ void RegScavenger::forward() {
     if (!MO.isReg())
       continue;
     unsigned Reg = MO.getReg();
-    if (!Reg || isReserved(Reg))
+    if (!Reg || isReserved(Reg) || !TRI->isInAllocatableClass(Reg))
       continue;
     if (MO.isUse()) {
       if (MO.isUndef())
diff --git a/test/CodeGen/X86/vector.ll b/test/CodeGen/X86/vector.ll
index 46b0e1890f1..4268d02c5a1 100644
--- a/test/CodeGen/X86/vector.ll
+++ b/test/CodeGen/X86/vector.ll
@@ -1,6 +1,6 @@
 ; Test that vectors are scalarized/lowered correctly.
 ; RUN: llc < %s -march=x86 -mcpu=i386 > %t
-; RUN: llc < %s -march=x86 -mcpu=yonah >> %t
+; RUN: llc < %s -march=x86 -mcpu=yonah -verify-machineinstrs >> %t
 
 %d8 = type <8 x double>
 %f1 = type <1 x float>