From: Duncan Sands <baldrick@free.fr>
Date: Fri, 11 Jul 2008 16:54:57 +0000 (+0000)
Subject: Port a shift-by-1 optimization from LegalizeDAG: it
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=edfba7e707a4f2f2e800843a7ef980c27d7f4eff;p=oota-llvm.git

Port a shift-by-1 optimization from LegalizeDAG: it
was presumably added after the rest of the code was
copied to LegalizeTypes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53459 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index a1840f130fc..4e3e21732b9 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1556,6 +1556,13 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
     } else if (Amt == NVTBits) {
       Lo = DAG.getConstant(0, NVT);
       Hi = InL;
+    } else if (Amt == 1) {
+      // Emit this X << 1 as X+X.
+      SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
+      SDOperand LoOps[2] = { InL, InL };
+      Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
+      SDOperand HiOps[3] = { InH, InH, Lo.getValue(1) };
+      Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
     } else {
       Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
       Hi = DAG.getNode(ISD::OR, NVT,
diff --git a/test/CodeGen/X86/2008-07-11-SHLBy1.ll b/test/CodeGen/X86/2008-07-11-SHLBy1.ll
new file mode 100644
index 00000000000..5b94a351cff
--- /dev/null
+++ b/test/CodeGen/X86/2008-07-11-SHLBy1.ll
@@ -0,0 +1,5 @@
+; RUN: llvm-as < %s | llc -march=x86-64 -o - | not grep shr
+define i128 @sl(i128 %x) {
+        %t = shl i128 %x, 1
+        ret i128 %t
+}