From: Roger Chen <roger.chen@rock-chips.com>
Date: Fri, 4 Mar 2016 06:19:03 +0000 (+0800)
Subject: ARM64: dts: rk3366-tb: correct reset pin for Ethernet PHY
X-Git-Tag: firefly_0821_release~3289
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=ed1a9bcb8ebd736e2416484274c39d3dea995355;p=firefly-linux-kernel-4.4.55.git

ARM64: dts: rk3366-tb: correct reset pin for Ethernet PHY

Change-Id: I94c1f22880965ab69865eeb81c0a33fa4f4201b4
Signed-off-by: Roger Chen <roger.chen@rock-chips.com>
---

diff --git a/arch/arm64/boot/dts/rockchip/rk3366-tb.dts b/arch/arm64/boot/dts/rockchip/rk3366-tb.dts
index 85b1fee3a54e..9ce246f5044e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3366-tb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3366-tb.dts
@@ -195,7 +195,7 @@
 	vcc_phy: vcc-phy-regulator {
 		compatible = "regulator-fixed";
 		enable-active-high;
-		gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+		gpio = <&gpio0 25 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&eth_phy_pwr>;
 		regulator-name = "vcc_phy";
@@ -610,12 +610,12 @@
 };
 
 &gmac {
-	phy_regulator = "vcc_phy";
+	phy-supply = <&vcc_phy>;
 	phy-mode = "rgmii";
 	clock_in_out = "input";
-	snps,reset-gpio = <&gpio2 15 0>;
+	snps,reset-gpio = <&gpio2 15 GPIO_ACTIVE_LOW>;
 	snps,reset-active-low;
-	snps,reset-delays-us = <0 10000 1000000>;
+	snps,reset-delays-us = <0 10000 50000>;
 	assigned-clocks = <&cru SCLK_MAC>;
 	assigned-clock-parents = <&ext_gmac>;
 	pinctrl-names = "default";