From: Eli Friedman <eli.friedman@gmail.com>
Date: Tue, 26 May 2009 19:18:56 +0000 (+0000)
Subject: Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=ecc23a5240a381ee15aca98301516d86eb09f1c6;p=oota-llvm.git

Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and
FP_TO_XINT.  Necessary for some cleanups I'm working on.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72431 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index cef87e9a498..864a914bba7 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -2304,7 +2304,7 @@ static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
     return ExpandLibCall(LC, Op, DAG, false, Dummy, TLI);
   }
 
-  return SDValue();
+  return Op;
 }
 
 //! Lower ISD::SINT_TO_FP, ISD::UINT_TO_FP for i32
@@ -2330,7 +2330,7 @@ static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
     return ExpandLibCall(LC, Op, DAG, false, Dummy, TLI);
   }
 
-  return SDValue();
+  return Op;
 }
 
 //! Lower ISD::SETCC
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index a1a95a50dc4..86bf70f8432 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -4595,10 +4595,10 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
 
   // These are really Legal; caller falls through into that case.
   if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
-    return SDValue();
+    return Op;
   if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
       Subtarget->is64Bit())
-    return SDValue();
+    return Op;
 
   DebugLoc dl = Op.getDebugLoc();
   unsigned Size = SrcVT.getSizeInBits()/8;
@@ -4795,7 +4795,7 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
   if (SrcVT == MVT::i64) {
     // We only handle SSE2 f64 target here; caller can handle the rest.
     if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
-      return SDValue();
+      return Op;
 
     return LowerUINT_TO_FP_i64(Op, DAG);
   } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
@@ -4881,7 +4881,7 @@ FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
   std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
   SDValue FIST = Vals.first, StackSlot = Vals.second;
-  if (FIST.getNode() == 0) return SDValue();
+  if (FIST.getNode() == 0) return Op;
 
   // Load the result.
   return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),