From: Colin LeMahieu Date: Wed, 3 Dec 2014 21:40:25 +0000 (+0000) Subject: [Hexagon] Converting member InstrDesc to static variable. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=ec42b051905ce166ae3a735430f79341f06a804f;p=oota-llvm.git [Hexagon] Converting member InstrDesc to static variable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223268 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Hexagon/HexagonMCInstLower.cpp b/lib/Target/Hexagon/HexagonMCInstLower.cpp index 5e4346d4021..3f5d6d84a10 100644 --- a/lib/Target/Hexagon/HexagonMCInstLower.cpp +++ b/lib/Target/Hexagon/HexagonMCInstLower.cpp @@ -42,7 +42,6 @@ static MCOperand GetSymbolRef(const MachineOperand& MO, const MCSymbol* Symbol, void llvm::HexagonLowerToMC(const MachineInstr* MI, HexagonMCInst& MCI, HexagonAsmPrinter& AP) { MCI.setOpcode(MI->getOpcode()); - MCI.setDesc(MI->getDesc()); for (unsigned i = 0, e = MI->getNumOperands(); i < e; i++) { const MachineOperand &MO = MI->getOperand(i); diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp index 18a596e9b67..d8b9a2567ee 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp @@ -18,8 +18,10 @@ using namespace llvm; -HexagonMCInst::HexagonMCInst() : MCInst(), MCID(nullptr) {} -HexagonMCInst::HexagonMCInst(MCInstrDesc const &mcid) : MCInst(), MCID(&mcid) {} +std::unique_ptr HexagonMCInst::MCII; + +HexagonMCInst::HexagonMCInst() : MCInst() {} +HexagonMCInst::HexagonMCInst(MCInstrDesc const &mcid) : MCInst() {} void HexagonMCInst::AppendImplicitOperands(MCInst &MCI) { MCI.addOperand(MCOperand::CreateImm(0)); @@ -75,16 +77,18 @@ unsigned HexagonMCInst::getUnits(const HexagonTargetMachine *TM) const { return (IS->getUnits()); } +MCInstrDesc const& HexagonMCInst::getDesc() const { return (MCII->get(getOpcode())); } + // Return the Hexagon ISA class for the insn. unsigned HexagonMCInst::getType() const { - const uint64_t F = MCID->TSFlags; + const uint64_t F = getDesc().TSFlags; return ((F >> HexagonII::TypePos) & HexagonII::TypeMask); } // Return whether the insn is an actual insn. bool HexagonMCInst::isCanon() const { - return (!MCID->isPseudo() && !isPrefix() && + return (!getDesc().isPseudo() && !isPrefix() && getType() != HexagonII::TypeENDLOOP); } @@ -95,25 +99,25 @@ bool HexagonMCInst::isPrefix() const { // Return whether the insn is solo, i.e., cannot be in a packet. bool HexagonMCInst::isSolo() const { - const uint64_t F = MCID->TSFlags; + const uint64_t F = getDesc().TSFlags; return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask); } // Return whether the insn is a new-value consumer. bool HexagonMCInst::isNewValue() const { - const uint64_t F = MCID->TSFlags; + const uint64_t F = getDesc().TSFlags; return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask); } // Return whether the instruction is a legal new-value producer. bool HexagonMCInst::hasNewValue() const { - const uint64_t F = MCID->TSFlags; + const uint64_t F = getDesc().TSFlags; return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask); } // Return the operand that consumes or produces a new value. const MCOperand &HexagonMCInst::getNewValue() const { - const uint64_t F = MCID->TSFlags; + const uint64_t F = getDesc().TSFlags; const unsigned O = (F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask; const MCOperand &MCO = getOperand(O); @@ -161,31 +165,31 @@ bool HexagonMCInst::isConstExtended(void) const { // Return whether the instruction must be always extended. bool HexagonMCInst::isExtended(void) const { - const uint64_t F = MCID->TSFlags; + const uint64_t F = getDesc().TSFlags; return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask; } // Return true if the instruction may be extended based on the operand value. bool HexagonMCInst::isExtendable(void) const { - const uint64_t F = MCID->TSFlags; + const uint64_t F = getDesc().TSFlags; return (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask; } // Return number of bits in the constant extended operand. unsigned HexagonMCInst::getBitCount(void) const { - const uint64_t F = MCID->TSFlags; + const uint64_t F = getDesc().TSFlags; return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask); } // Return constant extended operand number. unsigned short HexagonMCInst::getCExtOpNum(void) const { - const uint64_t F = MCID->TSFlags; + const uint64_t F = getDesc().TSFlags; return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask); } // Return whether the operand can be constant extended. bool HexagonMCInst::isOperandExtended(const unsigned short OperandNum) const { - const uint64_t F = MCID->TSFlags; + const uint64_t F = getDesc().TSFlags; return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask) == OperandNum; } @@ -193,7 +197,7 @@ bool HexagonMCInst::isOperandExtended(const unsigned short OperandNum) const { // Return the min value that a constant extendable operand can have // without being extended. int HexagonMCInst::getMinValue(void) const { - const uint64_t F = MCID->TSFlags; + const uint64_t F = getDesc().TSFlags; unsigned isSigned = (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask; unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask; @@ -207,7 +211,7 @@ int HexagonMCInst::getMinValue(void) const { // Return the max value that a constant extendable operand can have // without being extended. int HexagonMCInst::getMaxValue(void) const { - const uint64_t F = MCID->TSFlags; + const uint64_t F = getDesc().TSFlags; unsigned isSigned = (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask; unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask; diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h index f9acab70a9e..591109221d5 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h @@ -17,14 +17,16 @@ #include "HexagonTargetMachine.h" #include "llvm/MC/MCInst.h" +#include + +extern "C" void LLVMInitializeHexagonTargetMC(); namespace llvm { class MCOperand; class HexagonMCInst : public MCInst { - // MCID is set during instruction lowering. - // It is needed in order to access TSFlags for - // use in checking MC instruction properties. - const MCInstrDesc *MCID; + friend void ::LLVMInitializeHexagonTargetMC(); + // Used to access TSFlags + static std::unique_ptr MCII; public: explicit HexagonMCInst(); @@ -55,8 +57,7 @@ public: // Return the Hexagon ISA class for the insn. unsigned getType() const; - void setDesc(const MCInstrDesc &mcid) { MCID = &mcid; }; - const MCInstrDesc &getDesc(void) const { return *MCID; }; + MCInstrDesc const &getDesc() const; // Return whether the insn is an actual insn. bool isCanon() const; diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 14ddd9db327..ae5a22bdb01 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -14,6 +14,7 @@ #include "HexagonMCTargetDesc.h" #include "HexagonMCAsmInfo.h" #include "MCTargetDesc/HexagonInstPrinter.h" +#include "MCTargetDesc/HexagonMCInst.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCInstrInfo.h" @@ -115,6 +116,7 @@ extern "C" void LLVMInitializeHexagonTargetMC() { // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget, createHexagonMCInstrInfo); + HexagonMCInst::MCII.reset (createHexagonMCInstrInfo()); // Register the MC register info. TargetRegistry::RegisterMCRegInfo(TheHexagonTarget,