From: Peizhao Ou <peizhaoo@uci.edu>
Date: Wed, 4 Apr 2018 19:23:22 +0000 (-0700)
Subject: Adds comments for dmb approach (acquire loads and RMW load parts are not a problem... 
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=e73d167a1db6181e0166b732fbeee7c46aaee6f1;p=oota-llvm.git

Adds comments for dmb approach (acquire loads and RMW load parts are not a problem for subsequent stores
---

diff --git a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index cae2105bcf6..8f7d914a23b 100644
--- a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -1524,7 +1524,13 @@ bool AArch64LoadStoreOpt::tryToMergeLdStInst(
   return false;
 }
 
-static bool isLoad(MachineInstr* MI) {
+// XXX-comments: Returns true if this is a "normal" load, which refers to loads
+// that relaxed loads will be compiled to. This function is useful when we want
+// to extend the effect of a 'dmb ld' fence to subsequent stores (in the same
+// BB) that has not been interrupted by relaxed loads. Note that acquire loads
+// will be compiled to LDA*, and the load part of RMWs will be compiled to LDAX*
+// or LDX*, which would be in a different basic block.
+static bool isNormalLoad(MachineInstr* MI) {
   switch (MI->getOpcode()) {
     default: { return false; }
     case AArch64::LDRBBpost:
@@ -1688,7 +1694,7 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
         DEBUG(dbgs() << "Added barrier instruction\n\t" << *DMBInst
                      << "\n\tfor " << *MI << "\n");
         // Skip all the way till we reach the end of the basic block or a load.
-        while (MBBI != E && !isLoad(&*MBBI) && !isBranch(MBBI)) {
+        while (MBBI != E && !isNormalLoad(&*MBBI) && !isBranch(MBBI)) {
           MBBI++;
         }
         break;