From: Peizhao Ou Date: Thu, 5 Apr 2018 22:17:14 +0000 (-0700) Subject: Reverts those unnecessary changes in SelectionDAG & BranchFolding X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=e306a9bdc74e349c3406e2a6a08ad1c0afe709b6;p=oota-llvm.git Reverts those unnecessary changes in SelectionDAG & BranchFolding --- diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp index a56fec468cc..df5cac5a9f7 100644 --- a/lib/CodeGen/BranchFolding.cpp +++ b/lib/CodeGen/BranchFolding.cpp @@ -1116,12 +1116,6 @@ bool BranchFolder::OptimizeBranches(MachineFunction &MF) { for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end(); I != E; ) { MachineBasicBlock *MBB = &*I++; - // XXX-disabled: Don't optimize blocks that contain intentionally added fake - // conditional branch. - if (!MBB->getCanEliminateMachineBB()) { - continue; - } - MadeChange |= OptimizeBlock(MBB); // If it is dead, remove it. diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index f119023d217..c741982bc08 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -924,62 +924,6 @@ CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); APInt KnownZero, KnownOne; - - // XXX-disabled: - auto Opcode = Op.getOpcode(); - if (Opcode == ISD::AND || Opcode == ISD::OR) { - auto* Op1 = Op.getOperand(0).getNode(); - auto* Op2 = Op.getOperand(1).getNode(); - auto* Op1C = dyn_cast(Op1); - auto* Op2C = dyn_cast(Op2); - - // and X, 0 - if (Opcode == ISD::AND && !Op1C && Op2C && Op2C->isNullValue()) { - return false; - } - - // or (and X, 0), Y - if (Opcode == ISD::OR) { - if (Op1->getOpcode() == ISD::AND) { - auto* Op11 = Op1->getOperand(0).getNode(); - auto* Op12 = Op1->getOperand(1).getNode(); - auto* Op11C = dyn_cast(Op11); - auto* Op12C = dyn_cast(Op12); - if (!Op11C && Op12C && Op12C->isNullValue()) { - return false; - } - } - if (Op1->getOpcode() == ISD::TRUNCATE) { - // or (trunc (and %0, 0)), Y - auto* Op11 = Op1->getOperand(0).getNode(); - if (Op11->getOpcode() == ISD::AND) { - auto* Op111 = Op11->getOperand(0).getNode(); - auto* Op112 = Op11->getOperand(1).getNode(); - auto* Op111C = dyn_cast(Op111); - auto* Op112C = dyn_cast(Op112); - if (!Op111C && Op112C && Op112C->isNullValue()) { - // or (and X, 0), Y - return false; - } - } - } - } - } - - // trunc (and X, 0) - if (Opcode == ISD::TRUNCATE) { - auto* Op1 = Op.getOperand(0).getNode(); - if (Op1->getOpcode() == ISD::AND) { - auto* Op11 = Op1->getOperand(0).getNode(); - auto* Op12 = Op1->getOperand(1).getNode(); - auto* Op11C = dyn_cast(Op11); - auto* Op12C = dyn_cast(Op12); - if (!Op11C && Op12C && Op12C->isNullValue()) { - return false; - } - } - } - if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) return false; @@ -3098,22 +3042,6 @@ SDValue DAGCombiner::visitAND(SDNode *N) { // fold (and c1, c2) -> c1&c2 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0); ConstantSDNode *N1C = dyn_cast(N1); - - // XXX-disabled: (and x, 0) should not be folded. - // (and (and x, 0), y) shouldn't either. - if (!N0C && N1C && N1C->isNullValue()) { - return SDValue(); - } - if (!N0C) { - if (N0.getOpcode() == ISD::AND) { - auto* N01 = N0.getOperand(1).getNode(); - auto* N01C = dyn_cast(N01); - if (N01C && N01C->isNullValue()) { - return SDValue(); - } - } - } - if (N0C && N1C && !N1C->isOpaque()) return DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, N0C, N1C); // canonicalize constant to RHS diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index e845a9919ef..893871f9448 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3465,14 +3465,10 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, assert(VT.isInteger() && "This operator does not apply to FP types!"); assert(N1.getValueType() == N2.getValueType() && N1.getValueType() == VT && "Binary operator types must match!"); - - // XXX-disabled: - /* // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's // worth handling here. if (N2C && N2C->isNullValue()) return N2; - */ if (N2C && N2C->isAllOnesValue()) // X & -1 -> X return N1; break; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 491d7ec451c..c075da4738a 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -645,50 +645,6 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { // at this point. FuncInfo->clear(); - // XXX-update: Right after instruction selection, check through the - // intentionally added fake conditional branches and mark them as unremovable. - for (auto& MBB : *MF) { - // Check whether MBB has two successors which only contains an unconditional - // branch to the same destination. - if (MBB.succ_size() != 2 || - !MBB.getLastNonDebugInstr()->isUnconditionalBranch()) { - continue; - } - auto MBBSuccIter = MBB.succ_begin(); - auto* Succ1 = *MBBSuccIter; - MBBSuccIter++; - auto* Succ2 = *MBBSuccIter; - - MachineBasicBlock* Succ1Succ = nullptr; - MachineBasicBlock* Succ2Succ = nullptr; - if ((Succ1->size() == 1 && Succ1->begin()->isUnconditionalBranch()) || - (Succ1->size() == 0)) { - if (Succ1->succ_size()) { - Succ1Succ = *Succ1->succ_begin(); - } - } - if ((Succ2->size() == 1 && Succ2->begin()->isUnconditionalBranch()) || - (Succ2->size() == 0)) { - if (Succ1->succ_size()) { - Succ2Succ = *Succ2->succ_begin(); - } - } - - bool HasCommonDest = Succ1Succ && Succ1Succ == Succ2Succ; - if (HasCommonDest) { - auto MBBIter = MBB.end(); - std::advance(MBBIter, -2); - assert(MBBIter->isConditionalBranch()); - MBB.disableCanEliminateMachineBB(); - Succ1->disableCanEliminateMachineBB(); - Succ2->disableCanEliminateMachineBB(); - Succ1Succ->disableCanEliminateMachineBB(); - DEBUG(dbgs() << "Mark as unremovable machine basic block: " << MBB - << "\nMark as unremovable branch instruction: " << *MBBIter - << "\n"); - } - } - DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n"); DEBUG(MF->print(dbgs())); diff --git a/lib/IR/Verifier.cpp b/lib/IR/Verifier.cpp index 37b56f8efc7..9198b0e1fb5 100644 --- a/lib/IR/Verifier.cpp +++ b/lib/IR/Verifier.cpp @@ -1974,10 +1974,6 @@ void Verifier::visitBasicBlock(BasicBlock &BB) { "PHI nodes must have at least one entry. If the block is dead, " "the PHI should be removed!", PN); - if (PN->getNumIncomingValues() != Preds.size()) { - dbgs() << "Problematic function: \n" << *PN->getParent()->getParent() << "\n"; - dbgs() << "Problematic block: \n" << *PN->getParent() << "\n"; - } Assert(PN->getNumIncomingValues() == Preds.size(), "PHINode should have one entry for each predecessor of its " "parent basic block!", @@ -3358,9 +3354,6 @@ void Verifier::verifyDominatesUse(Instruction &I, unsigned i) { } const Use &U = I.getOperandUse(i); - if (!(InstsInThisBlock.count(Op) || DT.dominates(Op, U))) { - dbgs() << "Problematic function: \n" << *I.getParent()->getParent() << "\n"; - } Assert(InstsInThisBlock.count(Op) || DT.dominates(Op, U), "Instruction does not dominate all uses!", Op, &I); } diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp index 8cc3ff22725..c52c5544fc7 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -216,9 +216,6 @@ void AArch64PassConfig::addIRPasses() { // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg // ourselves. addPass(createAtomicExpandPass(TM)); - // XXX-update: Immediate add -licm pass after atomic expand pass to deal with - // loop invariants introduced mannually. -// addPass(createLICMPass()); // Cmpxchg instructions are often used with a subsequent comparison to // determine whether it succeeded. We can exploit existing control-flow in