From: Misha Brukman Date: Mon, 2 Jun 2003 21:16:54 +0000 (+0000) Subject: Added MOVR (move int reg on register condition), aka comparison with zero. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=e085a9d27928919fc0d23c1ad8c610fd231d26a9;p=oota-llvm.git Added MOVR (move int reg on register condition), aka comparison with zero. None of these instructions are actually used in the Sparc backend, so no changes were required in the instruction selector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6549 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/SparcV9/SparcV9.td b/lib/Target/SparcV9/SparcV9.td index d27430e6bdd..a1f52050269 100644 --- a/lib/Target/SparcV9/SparcV9.td +++ b/lib/Target/SparcV9/SparcV9.td @@ -448,8 +448,19 @@ def MOVFULEi : F4_4<2, 0b101100, 0b1110, "movfule">; // mova i/xcc, rs2, rd def MOVFOr : F4_3<2, 0b101100, 0b1111, "movfo">; // mova i/xcc, rs2, rd def MOVFOi : F4_4<2, 0b101100, 0b1111, "movfo">; // mova i/xcc, rs2, rd -// FIXME: Section A.36: Move Integer Register on Register Condition (MOVR) - +// Section A.36: Move Integer Register on Register Condition (MOVR) +def MOVRZr : F3_5<2, 0b101111, 0b001, "movrz">; // movrz rs1, rs2, rd +def MOVRZi : F3_6<2, 0b101111, 0b001, "movrz">; // movrz rs1, imm, rd +def MOVRLEZr : F3_5<2, 0b101111, 0b010, "movrlez">; // movrz rs1, rs2, rd +def MOVRLEZi : F3_6<2, 0b101111, 0b010, "movrlez">; // movrz rs1, imm, rd +def MOVRLZr : F3_5<2, 0b101111, 0b011, "movrlz">; // movrz rs1, rs2, rd +def MOVRLZi : F3_6<2, 0b101111, 0b011, "movrlz">; // movrz rs1, imm, rd +def MOVRNZr : F3_5<2, 0b101111, 0b101, "movrnz">; // movrz rs1, rs2, rd +def MOVRNZi : F3_6<2, 0b101111, 0b101, "movrnz">; // movrz rs1, imm, rd +def MOVRGZr : F3_5<2, 0b101111, 0b110, "movrgz">; // movrz rs1, rs2, rd +def MOVRGZi : F3_6<2, 0b101111, 0b110, "movrgz">; // movrz rs1, imm, rd +def MOVRGEZr : F3_5<2, 0b101111, 0b111, "movrgez">; // movrz rs1, rs2, rd +def MOVRGEZi : F3_6<2, 0b101111, 0b111, "movrgez">; // movrz rs1, imm, rd // Section A.37: Multiply and Divide (64-bit) - p199 def MULXr : F3_1<2, 0b001001, "mulx">; // mulx r, r, r diff --git a/lib/Target/SparcV9/SparcV9Instr.def b/lib/Target/SparcV9/SparcV9Instr.def index a2cc37d8e00..4ab37bdd562 100644 --- a/lib/Target/SparcV9/SparcV9Instr.def +++ b/lib/Target/SparcV9/SparcV9Instr.def @@ -235,12 +235,18 @@ I(FBULE, "fbule", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLA I(FBO , "fbo", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG) // Conditional move on integer comparison with zero. -I(MOVRZ , "movrz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) -I(MOVRLEZ, "movrlez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) -I(MOVRLZ , "movrlz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) -I(MOVRNZ , "movrnz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) -I(MOVRGZ , "movrgz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) -I(MOVRGEZ, "movrgez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) +I(MOVRZr , "movrz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) +I(MOVRZi , "movrz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) +I(MOVRLEZr, "movrlez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) +I(MOVRLEZi, "movrlez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) +I(MOVRLZr , "movrlz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) +I(MOVRLZi , "movrlz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) +I(MOVRNZr , "movrnz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) +I(MOVRNZi , "movrnz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) +I(MOVRGZr , "movrgz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) +I(MOVRGZi , "movrgz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) +I(MOVRGEZr, "movrgez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) +I(MOVRGEZi, "movrgez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG) // Conditional move on integer condition code. // The first argument specifies the ICC register: %icc or %xcc diff --git a/lib/Target/SparcV9/SparcV9_F3.td b/lib/Target/SparcV9/SparcV9_F3.td index ae8d06b33dd..160f431433a 100644 --- a/lib/Target/SparcV9/SparcV9_F3.td +++ b/lib/Target/SparcV9/SparcV9_F3.td @@ -142,6 +142,29 @@ class F3_4 opVal, bits<6> op3Val, string name> : F3_rs1simm13 { set Inst{12-0} = simm; } +class F3_5 opVal, bits<6> op3Val, bits<3> rcondVal, + string name> : F3_rs1rs2rd { + set op = opVal; + set op3 = op3Val; + set Name = name; + set Inst{13} = 0; // i field = 0 + set Inst{12-10} = rcondVal; // rcond field +} + +class F3_6 opVal, bits<6> op3Val, bits<3> rcondVal, + string name> : F3_rs1 { + bits<10> simm10; + bits<5> rd; + + set op = opVal; + set op3 = op3Val; + set Name = name; + set Inst{13} = 1; // i field = 1 + set Inst{12-10} = rcondVal; // rcond field +} + +//FIXME: classes 7-10 not defined!! + class F3_11 opVal, bits<6> op3Val, string name> : F3_rdrs1rs2 { bit x; set op = opVal;