From: Evan Cheng Date: Sat, 11 Jul 2009 06:37:27 +0000 (+0000) Subject: 80 col violation. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=dd6f63209cba0003e67470938830de2cb6917336;p=oota-llvm.git 80 col violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75358 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index f7e634a48cc..d7ba73c3e4b 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -588,8 +588,8 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, } if (DestRC == ARM::GPRRegisterClass) - AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)), DestReg) - .addReg(SrcReg))); + AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)), + DestReg).addReg(SrcReg))); else if (DestRC == ARM::SPRRegisterClass) AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FCPYS)), DestReg) .addReg(SrcReg));