From: Craig Topper <craig.topper@gmail.com>
Date: Tue, 1 May 2012 05:28:32 +0000 (+0000)
Subject: Make CLMUL and AES imply SSE2 since its needed to legalize the type.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=da1a984159ac673da06dc7d8f87dc81f673c5f49;p=oota-llvm.git

Make CLMUL and AES imply SSE2 since its needed to legalize the type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155888 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index 67b59b28d6c..14b6b246987 100644
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -87,7 +87,8 @@ def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
                                       "Enable AVX2 instructions",
                                       [FeatureAVX]>;
 def FeatureCLMUL   : SubtargetFeature<"clmul", "HasCLMUL", "true",
-                               "Enable carry-less multiplication instructions">;
+                               "Enable carry-less multiplication instructions",
+                               [FeatureSSE2]>;
 def FeatureFMA3    : SubtargetFeature<"fma3", "HasFMA3", "true",
                                       "Enable three-operand fused multiple-add",
                                       [FeatureAVX]>;
@@ -100,7 +101,8 @@ def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
                                           "HasVectorUAMem", "true",
                  "Allow unaligned memory operands on vector/SIMD instructions">;
 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
-                                      "Enable AES instructions">;
+                                      "Enable AES instructions",
+                                      [FeatureSSE2]>;
 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
                                       "Support MOVBE instruction">;
 def FeatureRDRAND  : SubtargetFeature<"rdrand", "HasRDRAND", "true",