From: 黄涛 Date: Fri, 17 Aug 2012 13:48:20 +0000 (+0800) Subject: Merge remote-tracking branch 'origin/develop-3.0-rk2928' into develop-3.0 X-Git-Tag: firefly_0821_release~8912 X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=d7fb2169b62bff9d8d19aa6a7e9cf5c97c4ebd7f;p=firefly-linux-kernel-4.4.55.git Merge remote-tracking branch 'origin/develop-3.0-rk2928' into develop-3.0 Conflicts: arch/arm/mach-rk30/include/mach/rk30_camera.h arch/arm/plat-rk/include/plat/rk_camera.h drivers/gpio/gpio-tps65910.c drivers/media/video/rk30_camera_oneframe.c drivers/mmc/host/rk29_sdmmc.c drivers/net/wireless/Kconfig drivers/net/wireless/Makefile drivers/net/wireless/wifi_sys/rkwifi_sys_iface.c drivers/regulator/rk30-pwm-regulator.c drivers/usb/dwc_otg/dwc_otg_driver.c drivers/usb/dwc_otg/dwc_otg_hcd.c drivers/usb/dwc_otg/dwc_otg_pcd.c sound/soc/codecs/Makefile sound/soc/rk29/Kconfig --- d7fb2169b62bff9d8d19aa6a7e9cf5c97c4ebd7f diff --cc arch/arm/configs/rk3066_sdk_defconfig index 45f44bbcccce,45f44bbcccce..0d91d95faf38 --- a/arch/arm/configs/rk3066_sdk_defconfig +++ b/arch/arm/configs/rk3066_sdk_defconfig @@@ -284,7 -284,7 +284,7 @@@ CONFIG_DISPLAY_SUPPORT= CONFIG_LCD_B101EW05=y CONFIG_FB_ROCKCHIP=y CONFIG_LCDC_RK30=y --CONFIG_HDMI_RK30=y ++CONFIG_RK_HDMI=y CONFIG_RGA_RK30=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set diff --cc arch/arm/configs/rk30_ds1001b_defconfig index b45a61f2dfcf,3d7f8ea4f641..b95b19713bab --- a/arch/arm/configs/rk30_ds1001b_defconfig +++ b/arch/arm/configs/rk30_ds1001b_defconfig @@@ -276,7 -277,7 +276,7 @@@ CONFIG_DISPLAY_SUPPORT= CONFIG_LCD_B101EW05=y CONFIG_FB_ROCKCHIP=y CONFIG_LCDC_RK30=y --CONFIG_HDMI_RK30=y ++CONFIG_RK_HDMI=y CONFIG_RGA_RK30=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set diff --cc arch/arm/configs/rk30_phonepad_defconfig index 9dd90e82d2ba,000000000000..41b7c36a5ea7 mode 100755,000000..100755 --- a/arch/arm/configs/rk30_phonepad_defconfig +++ b/arch/arm/configs/rk30_phonepad_defconfig @@@ -1,440 -1,0 +1,440 @@@ +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_LZO=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_PANIC_TIMEOUT=1 +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_ELF_CORE is not set +CONFIG_ASHMEM=y +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +# CONFIG_SLUB_DEBUG is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_ARCH_RK30=y +CONFIG_DDR_SDRAM_FREQ=300 +CONFIG_CLK_SWITCH_TO_32K=y +CONFIG_RK30_I2C_INSRAM=y +CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC=y +CONFIG_MACH_RK30_PHONE_PAD=y +# CONFIG_SWP_EMULATE is not set +CONFIG_FIQ_DEBUGGER=y +CONFIG_FIQ_DEBUGGER_NO_SLEEP=y +CONFIG_FIQ_DEBUGGER_CONSOLE=y +CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_SMP=y +# CONFIG_SMP_ON_UP is not set +CONFIG_NR_CPUS=2 +CONFIG_PREEMPT=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_COMPACTION=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_HOTPLUG=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_WAKELOCK=y +CONFIG_PM_RUNTIME=y +CONFIG_SUSPEND_TIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_INET_ESP=y +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_REJECT_SKERR=y +CONFIG_IP_NF_TARGET_LOG=y +CONFIG_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_TARGET_LOG=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE=y +# CONFIG_BRIDGE_IGMP_SNOOPING is not set +CONFIG_PHONET=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_U32=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=y +CONFIG_NET_ACT_MIRRED=y +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_MAC80211=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_RKNAND=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_MISC_DEVICES=y +CONFIG_UID_STAT=y +CONFIG_APANIC=y +CONFIG_3G_MODULE=y +CONFIG_MT6229=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_DM_UEVENT=y +CONFIG_NETDEVICES=y +CONFIG_PHYLIB=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_WLAN_80211=y +CONFIG_MT6620=y +CONFIG_USB_USBNET=y +CONFIG_PPP=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_MPPE=y +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYRESET=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_INPUT_TABLET=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_GT82X_IIC=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_KEYCHORD=y +CONFIG_INPUT_UINPUT=y +CONFIG_COMPASS_AK8975=y +CONFIG_GS_MMA8452=y +CONFIG_GS_LIS3DH=y +CONFIG_GYRO_L3G4200D=y +CONFIG_SENSOR_DEVICE=y +CONFIG_GSENSOR_DEVICE=y +CONFIG_GS_KXTIK=y +CONFIG_COMPASS_DEVICE=y +CONFIG_GYROSCOPE_DEVICE=y +# CONFIG_SERIO is not set +# CONFIG_CONSOLE_TRANSLATIONS is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_RK29=y +CONFIG_UART0_RK29=y +CONFIG_UART0_DMA_RK29=3 +CONFIG_UART3_RK29=y +CONFIG_UART3_CTS_RTS_RK29=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C0_CONTROLLER_RK30=y +CONFIG_I2C1_CONTROLLER_RK30=y +CONFIG_I2C2_CONTROLLER_RK30=y +CONFIG_I2C3_CONTROLLER_RK30=y +CONFIG_I2C4_CONTROLLER_RK30=y +CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET=y +CONFIG_GPIO_WM831X=y +CONFIG_EXPANDED_GPIO_NUM=0 +CONFIG_EXPANDED_GPIO_IRQ_NUM=0 +CONFIG_SPI_FPGA_GPIO_NUM=0 +CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0 +CONFIG_POWER_SUPPLY=y +CONFIG_WM831X_BACKUP=y +CONFIG_BATTERY_RK30_ADC=y +CONFIG_BATTERY_RK30_AC_CHARGE=y +CONFIG_BATTERY_RK30_VOL3V8=y +CONFIG_POWER_ON_CHARGER_DISPLAY=y +CONFIG_WM8326_VBAT_LOW_DETECTION=y +# CONFIG_HWMON is not set +CONFIG_MFD_TPS65910=y +CONFIG_MFD_WM831X_I2C=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_TPS65910=y +CONFIG_REGULATOR_WM831X=y +CONFIG_RK30_PWM_REGULATOR=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_VIDEO_DEV=y +CONFIG_SOC_CAMERA=y +CONFIG_SOC_CAMERA_SIV121D=y +CONFIG_SOC_CAMERA_SID130B=y +CONFIG_VIDEO_RK29=y +CONFIG_VIDEO_RK29_CAMMEM_ION=y +CONFIG_ION=y +CONFIG_ION_ROCKCHIP=y +CONFIG_FB=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_DISPLAY_SUPPORT=y +CONFIG_LCD_HV070WSA100=y +CONFIG_FB_ROCKCHIP=y +CONFIG_LCDC_RK30=y - CONFIG_HDMI_RK30=y ++CONFIG_RK_HDMI=y +CONFIG_RGA_RK30=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +CONFIG_SND_SOC=y +CONFIG_SND_RK29_SOC=y +CONFIG_SND_RK_SOC_I2S2_2CH=y +CONFIG_SND_I2S_DMA_EVENT_STATIC=y +CONFIG_SND_RK29_SOC_RT5623=y +CONFIG_SND_RK29_SOC_RT3261=y +CONFIG_SND_RK29_CODEC_SOC_SLAVE=y +CONFIG_HID_A4TECH=y +CONFIG_HID_ACRUX=y +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=y +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=y +CONFIG_HID_ELECOM=y +CONFIG_HID_EZKEY=y +CONFIG_HID_KEYTOUCH=y +CONFIG_HID_KYE=y +CONFIG_HID_UCLOGIC=y +CONFIG_HID_WALTOP=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LCPOWER=y +CONFIG_HID_LOGITECH=y +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWII_FF=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=y +CONFIG_HID_NTRIG=y +CONFIG_HID_ORTEK=y +CONFIG_HID_PANTHERLORD=y +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_PICOLCD=y +CONFIG_HID_QUANTA=y +CONFIG_HID_ROCCAT_ARVO=y +CONFIG_HID_ROCCAT_KONE=y +CONFIG_HID_ROCCAT_KONEPLUS=y +CONFIG_HID_ROCCAT_KOVAPLUS=y +CONFIG_HID_ROCCAT_PYRA=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_WACOM=y +CONFIG_HID_ZEROPLUS=y +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OTG_BLACKLIST_HUB=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_USI=y +CONFIG_USB_GADGET=y +CONFIG_USB20_HOST=y +CONFIG_USB20_OTG=y +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_EMBEDDED_SDIO=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_SDMMC_RK29=y +CONFIG_RK29_SDIO_IRQ_FROM_GPIO=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_SWITCH=y +CONFIG_SWITCH_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_WM831X=y +CONFIG_TPS65910_RTC=y +CONFIG_STAGING=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +# CONFIG_CMMB is not set +CONFIG_MTK_COMBO=y +CONFIG_MTK_COMBO_PLAT_PATH="rockchip" +CONFIG_MTK_COMBO_COMM=m +CONFIG_MTK_COMBO_BT_HW_TEST=m +CONFIG_MTK_COMBO_BT_HCI=m +CONFIG_MTK_COMBO_FM=m +CONFIG_MTK_COMBO_WIFI=m +CONFIG_MTK_GPS=m +CONFIG_MTK_COMBO_GPS=m +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_XATTR is not set +# CONFIG_DNOTIFY is not set +CONFIG_FUSE_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --cc arch/arm/configs/rk30_sdk_defconfig index d2f2685c37d7,8f168b32c02d..a32d9ff90161 --- a/arch/arm/configs/rk30_sdk_defconfig +++ b/arch/arm/configs/rk30_sdk_defconfig @@@ -288,7 -281,7 +288,7 @@@ CONFIG_DISPLAY_SUPPORT= CONFIG_LCD_B101EW05=y CONFIG_FB_ROCKCHIP=y CONFIG_LCDC_RK30=y --CONFIG_HDMI_RK30=y ++CONFIG_RK_HDMI=y CONFIG_RGA_RK30=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set diff --cc arch/arm/mach-rk30/Makefile index 3777e6549650,2d7b649a3627..356ad42dbb8f mode 100644,100755..100644 --- a/arch/arm/mach-rk30/Makefile +++ b/arch/arm/mach-rk30/Makefile diff --cc arch/arm/mach-rk30/include/mach/io.h index e9498626293e,99cbdf4b13ad..a16be19cd662 --- a/arch/arm/mach-rk30/include/mach/io.h +++ b/arch/arm/mach-rk30/include/mach/io.h @@@ -214,7 -231,16 +222,12 @@@ #define RK30_GPIO4_PHYS 0x20084000 #define RK30_GPIO4_BASE RK30_IO_TO_VIRT1(RK30_GPIO4_PHYS) #define RK30_GPIO4_SIZE SZ_16K -#endif -#ifdef CONFIG_ARCH_RK31 + #define RK31_GPS_PHYS 0x10230000 + #define RK31_GPS_SIZE SZ_64K + #define RK31_HSIC_PHYS 0x10240000 + #define RK31_HSIC_SIZE SZ_256K -#endif + #if CONFIG_RK_DEBUG_UART == 0 #define DEBUG_UART_PHYS RK30_UART0_PHYS #define DEBUG_UART_BASE RK30_UART0_BASE diff --cc arch/arm/mach-rk30/include/mach/rk30_camera.h index 38e771f81e8c,acb1ce975416..85391efff2e3 --- a/arch/arm/mach-rk30/include/mach/rk30_camera.h +++ b/arch/arm/mach-rk30/include/mach/rk30_camera.h @@@ -18,11 -18,12 +18,11 @@@ along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ - #ifndef __ASM_ARCH_CAMERA_RK30_H_ + #ifndef __ASM_ARCH_CAMERA_RK30_H_ - + #define __ASM_ARCH_CAMERA_RK30_H_ - #define __ASM_ARCH_CAMERA_RK29_H_ #ifdef CONFIG_ARCH_RK30 - #define RK29_CAM_DRV_NAME "rk-camera-rk30" + #define RK29_CAM_DRV_NAME "rk-camera-rk30" #define RK_SUPPORT_CIF0 1 #define RK_SUPPORT_CIF1 1 #endif diff --cc arch/arm/mach-rk30/io.c index 1998b9abbb6e,80b421e4c91b..bb8e81564443 mode 100755,100644..100755 --- a/arch/arm/mach-rk30/io.c +++ b/arch/arm/mach-rk30/io.c diff --cc arch/arm/plat-rk/Kconfig index 81f2ecdeb0dc,44e2df19011a..4d74efde0397 mode 100755,100644..100755 --- a/arch/arm/plat-rk/Kconfig +++ b/arch/arm/plat-rk/Kconfig @@@ -128,17 -119,9 +128,17 @@@ config WIFI_CONTROL_FUN help Enables Power/Reset/Carddetect function abstraction +config WIFI_COMBO_MODULE_CONTROL_FUNC + bool "Enable WiFi_combo_module control function abstraction" + help + Enables Power/Reset/Carddetect function abstraction + +endchoice + + config RK29_VPU tristate "VPU (Video Processing Unit) service driver in kernel" - depends on ARCH_RK29 || ARCH_RK30 + depends on ARCH_RK29 || ARCH_RK30 || ARCH_RK2928 default m config RK29_LAST_LOG diff --cc drivers/media/video/rk30_camera.c index 6d7c3766dca9,31e8a5bfa746..31e8a5bfa746 mode 100755,100644..100755 --- a/drivers/media/video/rk30_camera.c +++ b/drivers/media/video/rk30_camera.c diff --cc drivers/regulator/rk30-pwm-regulator.c index 8b914cd565cc,ce7aee35eee5..2019ef5a264c --- a/drivers/regulator/rk30-pwm-regulator.c +++ b/drivers/regulator/rk30-pwm-regulator.c @@@ -66,7 -66,10 +66,10 @@@ struct rk_pwm_dcdc #define pwm_read_reg(id, addr) __raw_readl(addr+(RK30_PWM01_BASE+(id>>1)*0x20000+id*0x10)) #elif defined(CONFIG_ARCH_RK29) #define pwm_write_reg(id, addr, val) __raw_writel(val, addr+(RK29_PWM_BASE+id*0x10)) -#define pwm_read_reg(id, addr) __raw_readl(addr+(RK29_PWM_BASE+id*0x10)) +#define pwm_read_reg(id, addr) __raw_readl(addr+(RK29_PWM_BASE+id*0x10)) + #elif defined(CONFIG_ARCH_RK2928) + #define pwm_write_reg(id, addr, val) __raw_writel(val, addr+(RK2928_PWM_BASE+id*0x10)) + #define pwm_read_reg(id, addr) __raw_readl(addr+(RK2928_PWM_BASE+id*0x10)) #endif const static int pwm_voltage_map[] = { @@@ -81,20 -84,19 +84,22 @@@ static int pwm_set_rate(struct pwm_plat u32 divh,divTotal; int id = pdata->pwm_id; unsigned long clkrate; - - if ( id >3 || id <0 ) - /* - if ( id >2 || id <0 ) -- { ++ ++#if defined(CONFIG_ARCH_RK29) || defined(CONFIG_ARCH_RK2928) ++ clkrate = clk_get_rate(pwm_clk[0]); ++#elif defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31) ++ if (id == 0 || id == 1) { ++ clkrate = clk_get_rate(pwm_clk[0]); ++ } else if (id== 2 || id == 3) { ++ clkrate = clk_get_rate(pwm_clk[1]); ++ } else { printk("%s:pwm id error,id=%d\n",__func__,id); return -1; } -- -- if((id==0) || (id == 1)) - */ -- clkrate = clk_get_rate(pwm_clk[0]); - else - clkrate = clk_get_rate(pwm_clk[1]); ++#endif - DBG("%s:id=%d,rate=%d,clkrate=%d\n",__func__,id,rate,clkrate); + DBG("%s:id=%d,rate=%d,clkrate=%d\n",__func__,id,rate,clkrate); - + if(rate == 0) { // iomux pwm to gpio @@@ -278,15 -280,15 +283,15 @@@ static int __devinit pwm_regulator_prob pdata->suspend_voltage = pdata->max_uV; dcdc = kzalloc(sizeof(struct rk_pwm_dcdc), GFP_KERNEL); -- if (dcdc == NULL) { -- dev_err(&pdev->dev, "Unable to allocate private data\n"); -- return -ENOMEM; ++ if (dcdc == NULL) { ++ dev_err(&pdev->dev, "Unable to allocate private data\n"); ++ return -ENOMEM; } snprintf(dcdc->name, sizeof(dcdc->name), "PWM_DCDC%d", id + 1); -- dcdc->desc.name = dcdc->name; -- dcdc->desc.id = id; -- dcdc->desc.type = REGULATOR_VOLTAGE; ++ dcdc->desc.name = dcdc->name; ++ dcdc->desc.id = id; ++ dcdc->desc.type = REGULATOR_VOLTAGE; dcdc->desc.n_voltages = ARRAY_SIZE(pwm_voltage_map); dcdc->desc.ops = &pwm_voltage_ops; dcdc->desc.owner = THIS_MODULE; @@@ -294,11 -296,11 +299,11 @@@ printk("%s:n_voltages=%d\n",__func__,dcdc->desc.n_voltages); dcdc->regulator = regulator_register(&dcdc->desc, &pdev->dev, pdata->init_data, dcdc); -- if (IS_ERR(dcdc->regulator)) { -- ret = PTR_ERR(dcdc->regulator); ++ if (IS_ERR(dcdc->regulator)) { ++ ret = PTR_ERR(dcdc->regulator); dev_err(&pdev->dev, "Failed to register PWM_DCDC%d: %d\n", -- id + 1, ret); -- goto err; ++ id + 1, ret); ++ goto err; } snprintf(gpio_name, sizeof(gpio_name), "PWM_DCDC%d", id + 1); @@@ -321,6 -323,13 +326,13 @@@ pwm_clk[1] = clk_get(NULL, "pwm23"); clk_enable(pwm_clk[1]); } + #elif defined(CONFIG_ARCH_RK2928) + pwm_clk[0] = clk_get(NULL, "pwm01"); + if (IS_ERR(pwm_clk[0])) { - printk("pwm_clk get error %p\n", pwm_clk[0]); ++ printk("pwm_clk get error %p\n", pwm_clk[0]); + return -EINVAL; + } + clk_enable(pwm_clk[0]); #endif g_dcdc = dcdc; diff --cc drivers/spi/Kconfig index 51fc9c9f56ab,769044ca1887..ffdaa9c4aa60 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@@ -426,7 -426,7 +426,7 @@@ config SPI_NUC90 config SPIM_RK29 tristate "RK SPI master controller core support" - depends on (ARCH_RK29 || ARCH_RK30) && SPI_MASTER - depends on (ARCH_RK29 || ARCH_RK30 || ARCH_RK2928) && SPI_MASTER ++ depends on PLAT_RK && SPI_MASTER help general driver for SPI controller core from RockChips diff --cc drivers/tty/serial/Kconfig index d3c690a3ddf9,3405977f4d43..950b98efebe1 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@@ -1558,16 -1550,12 +1558,16 @@@ config UART2_CTS_RTS_RK2 depends on UART2_RK29 && !ARCH_RK30 config UART2_DMA_RK29 - bool "Serial port 2 DMA support (EXPERIMENTAL)" + int "Serial port 2 DMA support (EXPERIMENTAL)" depends on UART2_RK29 - + default 0 + help + 1:enable dma tx + 2:enable dma rx + 3:both enable dma tx and rx config UART3_RK29 bool "Serial port 3 support" - depends on SERIAL_RK29 + depends on SERIAL_RK29 && !ARCH_RK2928 config UART3_CTS_RTS_RK29 bool "Serial port 3 CTS/RTS support" diff --cc drivers/usb/dwc_otg/dwc_otg_driver.c index e7bdd6d2d970,d802e279674f..bee2c69cc91b --- a/drivers/usb/dwc_otg/dwc_otg_driver.c +++ b/drivers/usb/dwc_otg/dwc_otg_driver.c @@@ -1257,8 -1257,8 +1257,8 @@@ static __devinit int dwc_otg_driver_pro } clk_enable(ahbclk); - regval &= ~(0x01<<14); // exit suspend. - regval |= (0x01<<13); // software control - regval &= ~(0x01<<14); // enter suspend. ++ regval &= ~(0x01<<14); // enter suspend. + regval |= (0x01<<13); // software control enable. *otg_phy_con1 = regval; udelay(3); diff --cc drivers/usb/dwc_otg/dwc_otg_pcd.c index 81456fd70dbd,5b962bf8657e..f2f62ef70cc8 --- a/drivers/usb/dwc_otg/dwc_otg_pcd.c +++ b/drivers/usb/dwc_otg/dwc_otg_pcd.c @@@ -1682,8 -1677,7 +1682,8 @@@ int dwc_otg20phy_suspend( int exitsuspe } if( !exitsuspend && (pcd->phy_suspend == 0)) { pcd->phy_suspend = 1; - *otg_phy_con1 = 0x55 |(0x7f<<16); // enter suspend. + *otg_phy_con1 = 0x55 |(0x7f<<16); // enter suspend. + // *otg_phy_con1 = 0x1D5 |(0x1ff<<16); // enter suspend. enable dm,dp debug_wlf @2012.8.10 udelay(3); clk_disable(pcd->otg_dev->phyclk); clk_disable(pcd->otg_dev->ahbclk); diff --cc drivers/video/backlight/Kconfig index 81056931d8c6,2050685c42d3..3b8d99cc9fb9 --- a/drivers/video/backlight/Kconfig +++ b/drivers/video/backlight/Kconfig @@@ -299,7 -299,7 +299,7 @@@ config BACKLIGHT_RK2818_B config BACKLIGHT_RK29_BL bool "rk backlight driver" - depends on BACKLIGHT_CLASS_DEVICE && (ARCH_RK29 || ARCH_RK30) - depends on BACKLIGHT_CLASS_DEVICE && (ARCH_RK29 || ARCH_RK30 || ARCH_RK31 || ARCH_RK2928) ++ depends on BACKLIGHT_CLASS_DEVICE && PLAT_RK default y help rk29 backlight support. diff --cc drivers/video/backlight/rk29_backlight.c index 95ca486472fb,1221d6740927..6ea850f95725 --- a/drivers/video/backlight/rk29_backlight.c +++ b/drivers/video/backlight/rk29_backlight.c @@@ -38,9 -38,14 +38,14 @@@ #define DBG(x...) #endif - #if defined(CONFIG_ARCH_RK30) -#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31) ++#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31) #define write_pwm_reg(id, addr, val) __raw_writel(val, addr+(RK30_PWM01_BASE+(id>>1)*0x20000)+id*0x10) #define read_pwm_reg(id, addr) __raw_readl(addr+(RK30_PWM01_BASE+(id>>1)*0x20000+id*0x10)) + + #elif defined(CONFIG_ARCH_RK2928) + #define write_pwm_reg(id, addr, val) __raw_writel(val, addr+(RK2928_PWM_BASE+id*0x10)) -#define read_pwm_reg(id, addr) __raw_readl(addr+(RK2928_PWM_BASE+id*0x10)) ++#define read_pwm_reg(id, addr) __raw_readl(addr+(RK2928_PWM_BASE+id*0x10)) + #elif defined(CONFIG_ARCH_RK29) #define write_pwm_reg(id, addr, val) __raw_writel(val, addr+(RK29_PWM_BASE+id*0x10)) #define read_pwm_reg(id, addr) __raw_readl(addr+(RK29_PWM_BASE+id*0x10)) @@@ -231,15 -203,16 +236,15 @@@ static int rk29_backlight_probe(struct return -ENODEV; } - #if defined(CONFIG_ARCH_RK29) pwm_clk = clk_get(NULL, "pwm"); - #elif defined(CONFIG_ARCH_RK30) + #elif defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31) || defined(CONFIG_ARCH_RK2928) if (id == 0 || id == 1) pwm_clk = clk_get(NULL, "pwm01"); else if (id == 2 || id == 3) pwm_clk = clk_get(NULL, "pwm23"); #endif -- if (IS_ERR(pwm_clk)) { ++ if (IS_ERR(pwm_clk) || !pwm_clk) { printk(KERN_ERR "failed to get pwm clock source\n"); return -ENODEV; } diff --cc drivers/video/logo/.gitignore index e48355f538fa,e48355f538fa..aa9df07088af --- a/drivers/video/logo/.gitignore +++ b/drivers/video/logo/.gitignore @@@ -1,6 -1,6 +1,7 @@@ # # Generated files # ++*_bmp.c *_mono.c *_vga16.c *_clut224.c diff --cc drivers/video/rockchip/Kconfig index 06cd988688dc,267b5b5a222e..44135b06fb19 mode 100644,100755..100755 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@@ -14,9 -14,15 +14,15 @@@ config FB_WIM help Support wimo + config LCDC_RK2928 - tristate "rk2928 lcdc support " - depends on FB_ROCKCHIP ++ tristate "rk2928 lcdc support" ++ depends on FB_ROCKCHIP && ARCH_RK2928 + help + Driver for rk2928 lcdc . + config LCDC_RK30 -- tristate "rk30 lcdc support " -- depends on FB_ROCKCHIP ++ tristate "rk30 lcdc support" ++ depends on FB_ROCKCHIP && ARCH_RK30 help Driver for rk30 lcdc .There are two lcd controllers on rk30 @@@ -34,6 -40,26 +40,26 @@@ config LCDC1_RK3 help Support rk30 lcdc1 if you say y here + config LCDC_RK31 - tristate "rk31 lcdc support " - depends on FB_ROCKCHIP ++ tristate "rk31 lcdc support" ++ depends on FB_ROCKCHIP && ARCH_RK31 + help + Driver for rk31 lcdc .There are two lcdc controllers on RK31 + + config LCDC0_RK31 + bool "lcdc0 support" + depends on LCDC_RK31 + default y + help + Support rk31 lcdc0 if you say y here + + config LCDC1_RK31 + bool "lcdc1 support" + depends on LCDC_RK31 + default y if HDMI_RK31 + help + Support rk31 lcdc1 if you say y here + config DUAL_DISP_IN_KERNEL bool "implement dual display in kernel" depends on FB_ROCKCHIP diff --cc drivers/video/rockchip/chips/rk30_lcdc.c index 21a1c4e5c0bf,21a1c4e5c0bf..819444db1d3f --- a/drivers/video/rockchip/chips/rk30_lcdc.c +++ b/drivers/video/rockchip/chips/rk30_lcdc.c @@@ -745,6 -745,6 +745,36 @@@ static int rk30_lcdc_fps_mgr(struct rk_ screen->ft = 1000/fps ; //one frame time in ms return fps; } ++ ++static int rk30_fb_layer_remap(struct rk_lcdc_device_driver *dev_drv, ++ enum fb_win_map_order order) ++{ ++ return 0; ++} ++ ++static int rk30_fb_get_layer(struct rk_lcdc_device_driver *dev_drv,const char *id) ++{ ++ int layer_id; ++ ++ mutex_lock(&dev_drv->fb_win_id_mutex); ++ if (!strcmp(id,"fb1") || !strcmp(id,"fb3")) ++ { ++ layer_id = 0; ++ } ++ else if (!strcmp(id,"fb0") || !strcmp(id,"fb2")) ++ { ++ layer_id = 1; ++ } ++ else ++ { ++ printk(KERN_ERR "%s: unsupported %s", __func__, id); ++ layer_id = -ENODEV; ++ } ++ mutex_unlock(&dev_drv->fb_win_id_mutex); ++ ++ return layer_id; ++} ++ int rk30_lcdc_early_suspend(struct rk_lcdc_device_driver *dev_drv) { struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); @@@ -846,6 -846,6 +876,8 @@@ static struct rk_lcdc_device_driver lcd .ovl_mgr = rk30_lcdc_ovl_mgr, .get_disp_info = rk30_lcdc_get_disp_info, .fps_mgr = rk30_lcdc_fps_mgr, ++ .fb_get_layer = rk30_fb_get_layer, ++ .fb_layer_remap = rk30_fb_layer_remap, }; #ifdef CONFIG_PM static int rk30_lcdc_suspend(struct platform_device *pdev, pm_message_t state) diff --cc drivers/video/rockchip/hdmi/chips/rk30/rk30_hdmi_hw.c index 000000000000,e8b5f1e74b74..5f1d2662cf23 mode 000000,100755..100755 --- a/drivers/video/rockchip/hdmi/chips/rk30/rk30_hdmi_hw.c +++ b/drivers/video/rockchip/hdmi/chips/rk30/rk30_hdmi_hw.c @@@ -1,0 -1,656 +1,666 @@@ + #include + #include + #include + #include "rk30_hdmi.h" + #include "rk30_hdmi_hw.h" + + static char edid_result = 0; + + static inline void delay100us(void) + { + msleep(1); + } + + int rk30_hdmi_initial(void) + { + int rc = HDMI_ERROR_SUCESS; + + hdmi->pwr_mode = PWR_SAVE_MODE_A; + hdmi->hdmi_removed = rk30_hdmi_removed ; + hdmi->control_output = rk30_hdmi_control_output; + hdmi->config_video = rk30_hdmi_config_video; + hdmi->config_audio = rk30_hdmi_config_audio; + hdmi->detect_hotplug = rk30_hdmi_detect_hotplug; + hdmi->read_edid = rk30_hdmi_read_edid; + // internal hclk = hdmi_hclk/20 + HDMIWrReg(0x800, HDMI_INTERANL_CLK_DIV); + + if(hdmi->hdcp_power_on_cb) + rc = hdmi->hdcp_power_on_cb(); + + return rc; + } + + static void rk30_hdmi_set_pwr_mode(int mode) + { + if(hdmi->pwr_mode == mode) + return; + hdmi_dbg(hdmi->dev, "[%s] mode %d\n", __FUNCTION__, mode); + switch(mode) + { + case PWR_SAVE_MODE_A: + HDMIWrReg(SYS_CTRL, 0x10); + break; + case PWR_SAVE_MODE_B: + HDMIWrReg(SYS_CTRL, 0x20); + break; + case PWR_SAVE_MODE_D: + // reset PLL A&B + HDMIWrReg(SYS_CTRL, 0x4C); + delay100us(); + // release PLL A reset + HDMIWrReg(SYS_CTRL, 0x48); + delay100us(); + // release PLL B reset + HDMIWrReg(SYS_CTRL, 0x40); + break; + case PWR_SAVE_MODE_E: + HDMIWrReg(SYS_CTRL, 0x80); + break; + } + hdmi->pwr_mode = mode; + if(mode != PWR_SAVE_MODE_A) + msleep(10); + hdmi_dbg(hdmi->dev, "[%s] curmode %02x\n", __FUNCTION__, HDMIRdReg(SYS_CTRL)); + } + + int rk30_hdmi_detect_hotplug(void) + { + int value = HDMIRdReg(HPD_MENS_STA); + + hdmi_dbg(hdmi->dev, "[%s] value %02x\n", __FUNCTION__, value); ++ #if 0 ++ // When HPD and TMDS_CLK was high, HDMI is actived. + value &= m_HOTPLUG_STATUS | m_MSEN_STATUS; + if(value == (m_HOTPLUG_STATUS | m_MSEN_STATUS) ) + return HDMI_HPD_ACTIVED; + else if(value) + return HDMI_HPD_INSERT; + else + return HDMI_HPD_REMOVED; ++ #else ++ // When HPD was high, HDMI is actived. ++ if(value & m_HOTPLUG_STATUS) ++ return HDMI_HPD_ACTIVED; ++ else if(value & m_MSEN_STATUS) ++ return HDMI_HPD_INSERT; ++ else ++ return HDMI_HPD_REMOVED; ++ #endif + } + + #define HDMI_EDID_DDC_CLK 90000 + int rk30_hdmi_read_edid(int block, unsigned char *buff) + { + int value, ret = -1, ddc_bus_freq = 0; + char interrupt = 0, trytime = 2; + unsigned long flags; + + hdmi_dbg(hdmi->dev, "[%s] block %d\n", __FUNCTION__, block); + spin_lock_irqsave(&hdmi->irq_lock, flags); + edid_result = 0; + spin_unlock_irqrestore(&hdmi->irq_lock, flags); + //Before Phy parameter was set, DDC_CLK is equal to PLLA freq which is 30MHz. + //Set DDC I2C CLK which devided from DDC_CLK to 100KHz. + ddc_bus_freq = (30000000/HDMI_EDID_DDC_CLK)/4; + HDMIWrReg(DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); + HDMIWrReg(DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF); + + // Enable edid interrupt + HDMIWrReg(INTR_MASK1, m_INT_HOTPLUG | m_INT_MSENS | m_INT_EDID_ERR | m_INT_EDID_READY); + + while(trytime--) { + // Config EDID block and segment addr + HDMIWrReg(EDID_WORD_ADDR, (block%2) * 0x80); + HDMIWrReg(EDID_SEGMENT_POINTER, block/2); + + value = 100; + while(value--) + { + spin_lock_irqsave(&hdmi->irq_lock, flags); + interrupt = edid_result; + edid_result = 0; + spin_unlock_irqrestore(&hdmi->irq_lock, flags); + if(interrupt & (m_INT_EDID_ERR | m_INT_EDID_READY)) + break; + msleep(10); + } + hdmi_dbg(hdmi->dev, "[%s] edid read value %d\n", __FUNCTION__, value); + if(interrupt & m_INT_EDID_READY) + { + for(value = 0; value < HDMI_EDID_BLOCK_SIZE; value++) + buff[value] = HDMIRdReg(DDC_READ_FIFO_ADDR); + ret = 0; + + hdmi_dbg(hdmi->dev, "[%s] edid read sucess\n", __FUNCTION__); + #ifdef HDMI_DEBUG + for(value = 0; value < 128; value++) { + printk("%02x ,", buff[value]); + if( (value + 1) % 16 == 0) + printk("\n"); + } + #endif + break; + } + if(interrupt & m_INT_EDID_ERR) + hdmi_err(hdmi->dev, "[%s] edid read error\n", __FUNCTION__); + + } + // Disable edid interrupt + HDMIWrReg(INTR_MASK1, m_INT_HOTPLUG | m_INT_MSENS); + // msleep(100); + return ret; + } + + static inline void rk30_hdmi_config_phy_reg(int reg, int value) + { + HDMIWrReg(reg, value); + HDMIWrReg(SYS_CTRL, 0x2C); + delay100us(); + HDMIWrReg(SYS_CTRL, 0x20); + msleep(1); + } + + static void rk30_hdmi_config_phy(unsigned char vic) + { + HDMIWrReg(DEEP_COLOR_MODE, 0x22); // tmds frequency same as input dlck + rk30_hdmi_set_pwr_mode(PWR_SAVE_MODE_B); + switch(vic) + { + case HDMI_1920x1080p_60Hz: + case HDMI_1920x1080p_50Hz: + rk30_hdmi_config_phy_reg(0x158, 0x0E); + rk30_hdmi_config_phy_reg(0x15c, 0x00); + rk30_hdmi_config_phy_reg(0x160, 0x60); + rk30_hdmi_config_phy_reg(0x164, 0x00); + rk30_hdmi_config_phy_reg(0x168, 0xDA); + rk30_hdmi_config_phy_reg(0x16c, 0xA1); + rk30_hdmi_config_phy_reg(0x170, 0x0e); + rk30_hdmi_config_phy_reg(0x174, 0x22); + rk30_hdmi_config_phy_reg(0x178, 0x00); + break; + + case HDMI_1920x1080i_60Hz: + case HDMI_1920x1080i_50Hz: + case HDMI_1280x720p_60Hz: + case HDMI_1280x720p_50Hz: + rk30_hdmi_config_phy_reg(0x158, 0x06); + rk30_hdmi_config_phy_reg(0x15c, 0x00); + rk30_hdmi_config_phy_reg(0x160, 0x60); + rk30_hdmi_config_phy_reg(0x164, 0x00); + rk30_hdmi_config_phy_reg(0x168, 0xCA); + rk30_hdmi_config_phy_reg(0x16c, 0xA3); + rk30_hdmi_config_phy_reg(0x170, 0x0e); + rk30_hdmi_config_phy_reg(0x174, 0x20); + rk30_hdmi_config_phy_reg(0x178, 0x00); + break; + + case HDMI_720x576p_50Hz_4_3: + case HDMI_720x576p_50Hz_16_9: + case HDMI_720x480p_60Hz_4_3: + case HDMI_720x480p_60Hz_16_9: + rk30_hdmi_config_phy_reg(0x158, 0x02); + rk30_hdmi_config_phy_reg(0x15c, 0x00); + rk30_hdmi_config_phy_reg(0x160, 0x60); + rk30_hdmi_config_phy_reg(0x164, 0x00); + rk30_hdmi_config_phy_reg(0x168, 0xC2); + rk30_hdmi_config_phy_reg(0x16c, 0xA2); + rk30_hdmi_config_phy_reg(0x170, 0x0e); + rk30_hdmi_config_phy_reg(0x174, 0x20); + rk30_hdmi_config_phy_reg(0x178, 0x00); + break; + default: + hdmi_err(hdmi->dev, "not support such vic %d\n", vic); + break; + } + } + + static void rk30_hdmi_config_avi(unsigned char vic, unsigned char output_color) + { + int i, clolorimetry, aspect_ratio; + char info[SIZE_AVI_INFOFRAME]; + + memset(info, 0, SIZE_AVI_INFOFRAME); + HDMIWrReg(CONTROL_PACKET_BUF_INDEX, INFOFRAME_AVI); + info[0] = 0x82; + info[1] = 0x02; + info[2] = 0x0D; + info[3] = info[0] + info[1] + info[2]; + + if(output_color == VIDEO_OUTPUT_YCBCR444) + info[4] = (AVI_COLOR_MODE_YCBCR444 << 5); + else if(output_color == VIDEO_OUTPUT_YCBCR422) + info[4] = (AVI_COLOR_MODE_YCBCR422 << 5); + else + info[4] = (AVI_COLOR_MODE_RGB << 5); + info[4] |= (1 << 4); //Enable active format data bits is present in info[2] + + switch(vic) + { + case HDMI_720x480i_60Hz_4_3: + case HDMI_720x576i_50Hz_4_3: + case HDMI_720x480p_60Hz_4_3: + case HDMI_720x576p_50Hz_4_3: + aspect_ratio = AVI_CODED_FRAME_ASPECT_4_3; + clolorimetry = AVI_COLORIMETRY_SMPTE_170M; + break; + case HDMI_720x480i_60Hz_16_9: + case HDMI_720x576i_50Hz_16_9: + case HDMI_720x480p_60Hz_16_9: + case HDMI_720x576p_50Hz_16_9: + aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9; + clolorimetry = AVI_COLORIMETRY_SMPTE_170M; + break; + default: + aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9; + clolorimetry = AVI_COLORIMETRY_ITU709; + } + + if(output_color == VIDEO_OUTPUT_RGB444) + clolorimetry = AVI_COLORIMETRY_NO_DATA; + + info[5] = (clolorimetry << 6) | (aspect_ratio << 4) | ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME; + info[6] = 0; + info[7] = vic; + info[8] = 0; + + // Calculate AVI InfoFrame ChecKsum + for (i = 4; i < SIZE_AVI_INFOFRAME; i++) + { + info[3] += info[i]; + } + info[3] = 0x100 - info[3]; + + for(i = 0; i < SIZE_AVI_INFOFRAME; i++) + HDMIWrReg(CONTROL_PACKET_HB0 + i*4, info[i]); + } + + static char coeff_csc[][24] = { + //G B R Bias + { //CSC_RGB_0_255_TO_ITU601_16_235 + 0x11, 0xb6, 0x02, 0x0b, 0x10, 0x55, 0x00, 0x80, //Cr + 0x02, 0x59, 0x01, 0x32, 0x00, 0x75, 0x00, 0x10, //Y + 0x11, 0x5b, 0x10, 0xb0, 0x02, 0x0b, 0x00, 0x80, //Cb + }, + { //CSC_RGB_0_255_TO_ITU709_16_235 + 0x11, 0xdb, 0x02, 0x0b, 0x10, 0x30, 0x00, 0x80, //Cr + 0x02, 0xdc, 0x00, 0xda, 0x00, 0x4a, 0x00, 0x10, //Y + 0x11, 0x93, 0x10, 0x78, 0x02, 0x0b, 0x00, 0x80, //Cb + }, + //Y Cr Cb Bias + { //CSC_ITU601_16_235_TO_RGB_16_235 + 0x04, 0x00, 0x05, 0x7c, 0x00, 0x00, 0x02, 0xaf, //R + 0x04, 0x00, 0x12, 0xcb, 0x11, 0x58, 0x00, 0x84, //G + 0x04, 0x00, 0x00, 0x00, 0x06, 0xee, 0x02, 0xde, //B + }, + { //CSC_ITU709_16_235_TO_RGB_16_235 + 0x04, 0x00, 0x06, 0x29, 0x00, 0x00, 0x02, 0xc5, //R + 0x04, 0x00, 0x11, 0xd6, 0x10, 0xbb, 0x00, 0x52, //G + 0x04, 0x00, 0x00, 0x00, 0x07, 0x44, 0x02, 0xe8, //B + }, + { //CSC_ITU601_16_235_TO_RGB_0_255 + 0x04, 0xa8, 0x05, 0x7c, 0x00, 0x00, 0x02, 0xc2, //R + 0x04, 0xa8, 0x12, 0xcb, 0x11, 0x58, 0x00, 0x72, //G + 0x04, 0xa8, 0x00, 0x00, 0x06, 0xee, 0x02, 0xf0, //B + }, + { //CSC_ITU709_16_235_TO_RGB_0_255 + 0x04, 0xa8, 0x06, 0x29, 0x00, 0x00, 0x02, 0xd8, //R + 0x04, 0xa8, 0x11, 0xd6, 0x10, 0xbb, 0x00, 0x40, //G + 0x04, 0xa8, 0x00, 0x00, 0x07, 0x44, 0x02, 0xfb, //B + }, + + }; + + static void rk30_hdmi_config_csc(struct hdmi_video_para *vpara) + { + int i, mode; + char *coeff = NULL; + + if( ((vpara->input_color == VIDEO_INPUT_COLOR_RGB) && (vpara->output_color == VIDEO_OUTPUT_RGB444)) || + ((vpara->input_color == VIDEO_INPUT_COLOR_YCBCR) && (vpara->output_color != VIDEO_OUTPUT_RGB444) )) + { + return; + } + switch(vpara->vic) + { + case HDMI_720x480i_60Hz_4_3: + case HDMI_720x576i_50Hz_4_3: + case HDMI_720x480p_60Hz_4_3: + case HDMI_720x576p_50Hz_4_3: + case HDMI_720x480i_60Hz_16_9: + case HDMI_720x576i_50Hz_16_9: + case HDMI_720x480p_60Hz_16_9: + case HDMI_720x576p_50Hz_16_9: + if(vpara->input_color == VIDEO_INPUT_COLOR_RGB) + mode = CSC_RGB_0_255_TO_ITU601_16_235; + else if(vpara->output_mode == OUTPUT_HDMI) + mode = CSC_ITU601_16_235_TO_RGB_16_235; + else + mode = CSC_ITU601_16_235_TO_RGB_0_255; + break; + default: + if(vpara->input_color == VIDEO_INPUT_COLOR_RGB) + mode = CSC_RGB_0_255_TO_ITU709_16_235; + else if(vpara->output_mode == OUTPUT_HDMI) + mode = CSC_ITU709_16_235_TO_RGB_16_235; + else + mode = CSC_ITU709_16_235_TO_RGB_0_255; + break; + } + + coeff = coeff_csc[mode]; + + HDMIWrReg(CSC_CONFIG1, v_CSC_MODE(CSC_MODE_MANUAL) | v_CSC_BRSWAP_DIABLE(1)); + + for(i = 0; i < 24; i++) + HDMIWrReg(CSC_PARA_C0_H + i*4, coeff[i]); + + HDMIWrReg(AV_CTRL2, v_CSC_ENABLE(1)); + } + + int rk30_hdmi_config_video(struct hdmi_video_para *vpara) + { + int value; + struct fb_videomode *mode; + + hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__); + if(vpara == NULL) { + hdmi_err(hdmi->dev, "[%s] input parameter error\n", __FUNCTION__); + return -1; + } + if(hdmi->pwr_mode == PWR_SAVE_MODE_E) + rk30_hdmi_set_pwr_mode(PWR_SAVE_MODE_D); + if(hdmi->pwr_mode == PWR_SAVE_MODE_D || hdmi->pwr_mode == PWR_SAVE_MODE_A) + rk30_hdmi_set_pwr_mode(PWR_SAVE_MODE_B); + + if(hdmi->hdcp_power_off_cb) + hdmi->hdcp_power_off_cb(); + + // Input video mode is RGB24bit, Data enable signal from external + HDMIMskReg(value, AV_CTRL1, m_INPUT_VIDEO_MODE | m_DE_SIGNAL_SELECT, \ + v_INPUT_VIDEO_MODE(vpara->input_mode) | EXTERNAL_DE) + HDMIMskReg(value, VIDEO_CTRL1, m_VIDEO_OUTPUT_MODE | m_VIDEO_INPUT_DEPTH | m_VIDEO_INPUT_COLOR_MODE, \ + v_VIDEO_OUTPUT_MODE(vpara->output_color) | v_VIDEO_INPUT_DEPTH(VIDEO_INPUT_DEPTH_8BIT) | vpara->input_color) + HDMIWrReg(DEEP_COLOR_MODE, 0x20); + // color space convert + rk30_hdmi_config_csc(vpara); + // Set HDMI Mode + HDMIWrReg(HDCP_CTRL, v_HDMI_DVI(vpara->output_mode)); + + // Set ext video + mode = (struct fb_videomode *)hdmi_vic_to_videomode(vpara->vic); + if(mode == NULL) + { + hdmi_err(hdmi->dev, "[%s] not found vic %d\n", __FUNCTION__, vpara->vic); + return -ENOENT; + } + hdmi->tmdsclk = mode->pixclock; + + if( (vpara->vic == HDMI_720x480p_60Hz_4_3) || (vpara->vic == HDMI_720x480p_60Hz_16_9) ) + value = v_VSYNC_OFFSET(6); + else + value = v_VSYNC_OFFSET(0); + value |= v_EXT_VIDEO_ENABLE(1) | v_INTERLACE(mode->vmode); + if(mode->sync & FB_SYNC_HOR_HIGH_ACT) + value |= v_HSYNC_POLARITY(1); + if(mode->sync & FB_SYNC_VERT_HIGH_ACT) + value |= v_VSYNC_POLARITY(1); + HDMIWrReg(EXT_VIDEO_PARA, value); + value = mode->left_margin + mode->xres + mode->right_margin + mode->hsync_len; + HDMIWrReg(EXT_VIDEO_PARA_HTOTAL_L, value & 0xFF); + HDMIWrReg(EXT_VIDEO_PARA_HTOTAL_H, (value >> 8) & 0xFF); + + value = mode->left_margin + mode->right_margin + mode->hsync_len; + HDMIWrReg(EXT_VIDEO_PARA_HBLANK_L, value & 0xFF); + HDMIWrReg(EXT_VIDEO_PARA_HBLANK_H, (value >> 8) & 0xFF); + + value = mode->left_margin + mode->hsync_len; + HDMIWrReg(EXT_VIDEO_PARA_HDELAY_L, value & 0xFF); + HDMIWrReg(EXT_VIDEO_PARA_HDELAY_H, (value >> 8) & 0xFF); + + value = mode->hsync_len; + HDMIWrReg(EXT_VIDEO_PARA_HSYNCWIDTH_L, value & 0xFF); + HDMIWrReg(EXT_VIDEO_PARA_HSYNCWIDTH_H, (value >> 8) & 0xFF); + + value = mode->upper_margin + mode->yres + mode->lower_margin + mode->vsync_len; + HDMIWrReg(EXT_VIDEO_PARA_VTOTAL_L, value & 0xFF); + HDMIWrReg(EXT_VIDEO_PARA_VTOTAL_H, (value >> 8) & 0xFF); + + value = mode->upper_margin + mode->vsync_len + mode->lower_margin; + HDMIWrReg(EXT_VIDEO_PARA_VBLANK_L, value & 0xFF); + + if(vpara->vic == HDMI_720x480p_60Hz_4_3 || vpara->vic == HDMI_720x480p_60Hz_16_9) + value = 42; + else + value = mode->upper_margin + mode->vsync_len; + + HDMIWrReg(EXT_VIDEO_PARA_VDELAY, value & 0xFF); + + value = mode->vsync_len; + HDMIWrReg(EXT_VIDEO_PARA_VSYNCWIDTH, value & 0xFF); + + if(vpara->output_mode == OUTPUT_HDMI) { + rk30_hdmi_config_avi(vpara->vic, vpara->output_color); + hdmi_dbg(hdmi->dev, "[%s] sucess output HDMI.\n", __FUNCTION__); + } + else { + hdmi_dbg(hdmi->dev, "[%s] sucess output DVI.\n", __FUNCTION__); + } + + rk30_hdmi_config_phy(vpara->vic); + rk30_hdmi_control_output(0); + return 0; + } + + static void rk30_hdmi_config_aai(void) + { + int i; + char info[SIZE_AUDIO_INFOFRAME]; + + memset(info, 0, SIZE_AUDIO_INFOFRAME); + + info[0] = 0x84; + info[1] = 0x01; + info[2] = 0x0A; + + info[3] = info[0] + info[1] + info[2]; + for (i = 4; i < SIZE_AUDIO_INFOFRAME; i++) + info[3] += info[i]; + + info[3] = 0x100 - info[3]; + + HDMIWrReg(CONTROL_PACKET_BUF_INDEX, INFOFRAME_AAI); + for(i = 0; i < SIZE_AUDIO_INFOFRAME; i++) + HDMIWrReg(CONTROL_PACKET_HB0 + i*4, info[i]); + } + + int rk30_hdmi_config_audio(struct hdmi_audio *audio) + { + int value, rate, N; + char word_length, channel; + + if(audio->channel < 3) + channel = I2S_CHANNEL_1_2; + else if(audio->channel < 5) + channel = I2S_CHANNEL_3_4; + else if(audio->channel < 7) + channel = I2S_CHANNEL_5_6; + else + channel = I2S_CHANNEL_7_8; + + switch(audio->rate) + { + case HDMI_AUDIO_FS_32000: + rate = AUDIO_32K; + N = N_32K; + break; + case HDMI_AUDIO_FS_44100: + rate = AUDIO_441K; + N = N_441K; + break; + case HDMI_AUDIO_FS_48000: + rate = AUDIO_48K; + N = N_48K; + break; + case HDMI_AUDIO_FS_88200: + rate = AUDIO_882K; + N = N_882K; + break; + case HDMI_AUDIO_FS_96000: + rate = AUDIO_96K; + N = N_96K; + break; + case HDMI_AUDIO_FS_176400: + rate = AUDIO_1764K; + N = N_1764K; + break; + case HDMI_AUDIO_FS_192000: + rate = AUDIO_192K; + N = N_192K; + break; + default: + hdmi_err(hdmi->dev, "[%s] not support such sample rate %d\n", __FUNCTION__, audio->rate); + return -ENOENT; + } + // switch(audio->word_length) + // { + // case HDMI_AUDIO_WORD_LENGTH_16bit: + // word_length = 0x02; + // break; + // case HDMI_AUDIO_WORD_LENGTH_20bit: + // word_length = 0x0a; + // break; + // case HDMI_AUDIO_WORD_LENGTH_24bit: + // word_length = 0x0b; + // break; + // default: + // hdmi_err(hdmi->dev, "[%s] not support such word length %d\n", __FUNCTION__, audio->word_length); + // return -ENOENT; + // } + //set_audio_if I2S + HDMIWrReg(AUDIO_CTRL1, 0x00); //internal CTS, disable down sample, i2s input, disable MCLK + HDMIWrReg(AUDIO_CTRL2, 0x40); + HDMIWrReg(I2S_AUDIO_CTRL, v_I2S_MODE(I2S_MODE_STANDARD) | v_I2S_CHANNEL(channel) ); + HDMIWrReg(I2S_INPUT_SWAP, 0x00); //no swap + HDMIMskReg(value, AV_CTRL1, m_AUDIO_SAMPLE_RATE, v_AUDIO_SAMPLE_RATE(rate)) + // HDMIWrReg(SRC_NUM_AUDIO_LEN, word_length); + + //Set N value 6144, fs=48kHz + HDMIWrReg(N_1, N & 0xFF); + HDMIWrReg(N_2, (N >> 8) & 0xFF); + HDMIWrReg(LR_SWAP_N3, (N >> 16) & 0x0F); + + rk30_hdmi_config_aai(); + return 0; + } + + static void rk30_hdmi_audio_reset(void) + { + int value; + + HDMIMskReg(value, VIDEO_SETTING2, m_AUDIO_RESET, AUDIO_CAPTURE_RESET) + msleep(1); + HDMIMskReg(value, VIDEO_SETTING2, m_AUDIO_RESET, 0) + } + + void rk30_hdmi_control_output(int enable) + { + hdmi_dbg(hdmi->dev, "[%s] %d\n", __FUNCTION__, enable); + if(enable == 0) { - HDMIWrReg(AV_MUTE, v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1)); ++ HDMIWrReg(VIDEO_SETTING2, 0x03); + } + else { - HDMIWrReg(VIDEO_SETTING2, 0x03); + if(hdmi->pwr_mode == PWR_SAVE_MODE_B) { + // Switch to power save mode_d + rk30_hdmi_set_pwr_mode(PWR_SAVE_MODE_D); + } + if(hdmi->pwr_mode == PWR_SAVE_MODE_D) { + // Switch to power save mode_e + rk30_hdmi_set_pwr_mode(PWR_SAVE_MODE_E); + } + HDMIWrReg(VIDEO_SETTING2, 0x00); + rk30_hdmi_audio_reset(); + } + } + + int rk30_hdmi_removed(void) + { + if(hdmi->pwr_mode == PWR_SAVE_MODE_E) + { + HDMIWrReg(VIDEO_SETTING2, 0x00); + rk30_hdmi_audio_reset(); + rk30_hdmi_set_pwr_mode(PWR_SAVE_MODE_D); + } + if(hdmi->pwr_mode == PWR_SAVE_MODE_D) + rk30_hdmi_set_pwr_mode(PWR_SAVE_MODE_B); + if(hdmi->pwr_mode == PWR_SAVE_MODE_B && hdmi->state == HDMI_SLEEP) + { + HDMIWrReg(INTR_MASK1, m_INT_HOTPLUG | m_INT_MSENS); + HDMIWrReg(INTR_MASK2, 0); + HDMIWrReg(INTR_MASK3, 0); + HDMIWrReg(INTR_MASK4, 0); + // Disable color space convertion + HDMIWrReg(AV_CTRL2, v_CSC_ENABLE(0)); + HDMIWrReg(CSC_CONFIG1, v_CSC_MODE(CSC_MODE_AUTO) | v_CSC_BRSWAP_DIABLE(1)); + if(hdmi->hdcp_power_off_cb) + hdmi->hdcp_power_off_cb(); + rk30_hdmi_set_pwr_mode(PWR_SAVE_MODE_A); + } + dev_printk(KERN_INFO , hdmi->dev , "Removed.\n"); + return HDMI_ERROR_SUCESS; + } + + + irqreturn_t hdmi_irq(int irq, void *priv) + { + char interrupt1 = 0, interrupt2 = 0, interrupt3 = 0, interrupt4 = 0; + + if(hdmi->pwr_mode == PWR_SAVE_MODE_A) + { + HDMIWrReg(SYS_CTRL, 0x20); + hdmi->pwr_mode = PWR_SAVE_MODE_B; + + hdmi_dbg(hdmi->dev, "hdmi irq wake up\n"); + // HDMI was inserted when system is sleeping, irq was triggered only once + // when wake up. So we need to check hotplug status. + if(HDMIRdReg(HPD_MENS_STA) & (m_HOTPLUG_STATUS | m_MSEN_STATUS)) { + queue_delayed_work(hdmi->workqueue, &hdmi->delay_work, msecs_to_jiffies(10)); + } + } + else + { + interrupt1 = HDMIRdReg(INTR_STATUS1); + interrupt2 = HDMIRdReg(INTR_STATUS2); + interrupt3 = HDMIRdReg(INTR_STATUS3); + interrupt4 = HDMIRdReg(INTR_STATUS4); + HDMIWrReg(INTR_STATUS1, interrupt1); + HDMIWrReg(INTR_STATUS2, interrupt2); + HDMIWrReg(INTR_STATUS3, interrupt3); + HDMIWrReg(INTR_STATUS4, interrupt4); + #if 0 + hdmi_dbg(hdmi->dev, "[%s] interrupt1 %02x interrupt2 %02x interrupt3 %02x interrupt4 %02x\n",\ + __FUNCTION__, interrupt1, interrupt2, interrupt3, interrupt4); + #endif + if(interrupt1 & (m_INT_HOTPLUG | m_INT_MSENS)) + { + if(hdmi->state == HDMI_SLEEP) + hdmi->state = WAIT_HOTPLUG; + interrupt1 &= ~(m_INT_HOTPLUG | m_INT_MSENS); + queue_delayed_work(hdmi->workqueue, &hdmi->delay_work, msecs_to_jiffies(10)); + } + else if(interrupt1 & (m_INT_EDID_READY | m_INT_EDID_ERR)) { + spin_lock(&hdmi->irq_lock); + edid_result = interrupt1; + spin_unlock(&hdmi->irq_lock); + } + else if(hdmi->state == HDMI_SLEEP) { + hdmi_dbg(hdmi->dev, "hdmi return to sleep mode\n"); + HDMIWrReg(SYS_CTRL, 0x10); + hdmi->pwr_mode = PWR_SAVE_MODE_A; + } + if(interrupt2 && hdmi->hdcp_irq_cb) + hdmi->hdcp_irq_cb(interrupt2); + } + return IRQ_HANDLED; + } + diff --cc drivers/video/rockchip/hdmi/rk_hdmi_edid.c index 000000000000,ff44f4898f34..6a7d33f10790 mode 000000,100755..100755 --- a/drivers/video/rockchip/hdmi/rk_hdmi_edid.c +++ b/drivers/video/rockchip/hdmi/rk_hdmi_edid.c @@@ -1,0 -1,409 +1,409 @@@ + #include "rk_hdmi.h" + #include "../../edid.h" + + #define hdmi_edid_error(fmt, ...) \ + printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) + + #if 0 + #define hdmi_edid_debug(fmt, ...) \ + printk(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__) + #else + #define hdmi_edid_debug(fmt, ...) + #endif + + typedef enum HDMI_EDID_ERRORCODE + { + E_HDMI_EDID_SUCCESS = 0, + E_HDMI_EDID_PARAM, + E_HDMI_EDID_HEAD, + E_HDMI_EDID_CHECKSUM, + E_HDMI_EDID_VERSION, + E_HDMI_EDID_UNKOWNDATA, + E_HDMI_EDID_NOMEMORY + }HDMI_EDID_ErrorCode; + + static const unsigned int double_aspect_vic[] = {3, 7, 9, 11, 13, 15, 18, 22, 24, 26, 28, 30, 36, 38, 43, 45, 49, 51, 53, 55, 57, 59}; + static int hdmi_edid_checksum(unsigned char *buf) + { + int i; + int checksum = 0; + + for(i = 0; i < HDMI_EDID_BLOCK_SIZE; i++) + checksum += buf[i]; + + checksum &= 0xff; + + if(checksum == 0) + return E_HDMI_EDID_SUCCESS; + else + return E_HDMI_EDID_CHECKSUM; + } + + /* + @Des Parse Detail Timing Descriptor. + @Param buf : pointer to DTD data. + @Param pvic: VIC of DTD descripted. + */ + static int hdmi_edid_parse_dtd(unsigned char *block, struct fb_videomode *mode) + { + mode->xres = H_ACTIVE; + mode->yres = V_ACTIVE; + mode->pixclock = PIXEL_CLOCK; + // mode->pixclock /= 1000; + // mode->pixclock = KHZ2PICOS(mode->pixclock); + mode->right_margin = H_SYNC_OFFSET; + mode->left_margin = (H_ACTIVE + H_BLANKING) - + (H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH); + mode->upper_margin = V_BLANKING - V_SYNC_OFFSET - + V_SYNC_WIDTH; + mode->lower_margin = V_SYNC_OFFSET; + mode->hsync_len = H_SYNC_WIDTH; + mode->vsync_len = V_SYNC_WIDTH; + if (HSYNC_POSITIVE) + mode->sync |= FB_SYNC_HOR_HIGH_ACT; + if (VSYNC_POSITIVE) + mode->sync |= FB_SYNC_VERT_HIGH_ACT; + mode->refresh = PIXEL_CLOCK/((H_ACTIVE + H_BLANKING) * + (V_ACTIVE + V_BLANKING)); + if (INTERLACED) { + mode->yres *= 2; + mode->upper_margin *= 2; + mode->lower_margin *= 2; + mode->vsync_len *= 2; + mode->vmode |= FB_VMODE_INTERLACED; + } + mode->flag = FB_MODE_IS_DETAILED; + + hdmi_edid_debug("<<<<<<<>>>>>>>>\n"); + hdmi_edid_debug("%d KHz Refresh %d Hz", PIXEL_CLOCK/1000, mode->refresh); + hdmi_edid_debug("%d %d %d %d ", H_ACTIVE, H_ACTIVE + H_SYNC_OFFSET, + H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH, H_ACTIVE + H_BLANKING); + hdmi_edid_debug("%d %d %d %d ", V_ACTIVE, V_ACTIVE + V_SYNC_OFFSET, + V_ACTIVE + V_SYNC_OFFSET + V_SYNC_WIDTH, V_ACTIVE + V_BLANKING); + hdmi_edid_debug("%sHSync %sVSync\n\n", (HSYNC_POSITIVE) ? "+" : "-", + (VSYNC_POSITIVE) ? "+" : "-"); + return E_HDMI_EDID_SUCCESS; + } + + static int hdmi_edid_parse_base(unsigned char *buf, int *extend_num, struct hdmi_edid *pedid) + { + int rc, i; + + if(buf == NULL || extend_num == NULL) + return E_HDMI_EDID_PARAM; + + #ifdef DEBUG + for(i = 0; i < HDMI_EDID_BLOCK_SIZE; i++) + { + hdmi_edid_debug("%02x ", buf[i]&0xff); + if((i+1) % 16 == 0) + hdmi_edid_debug("\n"); + } + #endif + + // Check first 8 byte to ensure it is an edid base block. + if( buf[0] != 0x00 || + buf[1] != 0xFF || + buf[2] != 0xFF || + buf[3] != 0xFF || + buf[4] != 0xFF || + buf[5] != 0xFF || + buf[6] != 0xFF || + buf[7] != 0x00) + { + hdmi_edid_error("[EDID] check header error\n"); + return E_HDMI_EDID_HEAD; + } + + *extend_num = buf[0x7e]; + #ifdef DEBUG + hdmi_edid_debug("[EDID] extend block num is %d\n", buf[0x7e]); + #endif + + // Checksum + rc = hdmi_edid_checksum(buf); + if( rc != E_HDMI_EDID_SUCCESS) + { + hdmi_edid_error("[EDID] base block checksum error\n"); + return E_HDMI_EDID_CHECKSUM; + } + + pedid->specs = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL); + if(pedid->specs == NULL) + return E_HDMI_EDID_NOMEMORY; + + fb_edid_to_monspecs(buf, pedid->specs); + + return E_HDMI_EDID_SUCCESS; + } + + // Parse CEA Short Video Descriptor + static int hdmi_edid_get_cea_svd(unsigned char *buf, struct hdmi_edid *pedid) + { + const struct fb_videomode *mode; + int count, i, j, vic; + + count = buf[0] & 0x1F; + for(i = 0; i < count; i++) + { + hdmi_edid_debug("[EDID-CEA] %02x VID %d native %d\n", buf[1 + i], buf[1 + i] & 0x7f, buf[1 + i] >> 7); + vic = buf[1 + i] & 0x7f; + for(j = 0; j < ARRAY_SIZE(double_aspect_vic); j++) + { + if(vic == double_aspect_vic[j]) + { + vic--; + break; + } + } + if(vic) + { + mode = hdmi_vic_to_videomode(vic); + if(mode) + { + hdmi_add_videomode(mode, &pedid->modelist); + } + } + } + return 0; + } + + // Parse CEA Short Audio Descriptor + static int hdmi_edid_parse_cea_sad(unsigned char *buf, struct hdmi_edid *pedid) + { + int i, count; + + count = buf[0] & 0x1F; + pedid->audio = kmalloc((count/3)*sizeof(struct hdmi_audio), GFP_KERNEL); + if(pedid->audio == NULL) + return E_HDMI_EDID_NOMEMORY; + pedid->audio_num = count/3; + for(i = 0; i < pedid->audio_num; i++) + { + pedid->audio[i].type = (buf[1 + i*3] >> 3) & 0x0F; + pedid->audio[i].channel = (buf[1 + i*3] & 0x07) + 1; + pedid->audio[i].rate = buf[1 + i*3 + 1]; + if(pedid->audio[i].type == HDMI_AUDIO_LPCM)//LPCM + { + pedid->audio[i].word_length = buf[1 + i*3 + 2]; + } + // printk("[EDID-CEA] type %d channel %d rate %d word length %d\n", + // pedid->audio[i].type, pedid->audio[i].channel, pedid->audio[i].rate, pedid->audio[i].word_length); + } + return E_HDMI_EDID_SUCCESS; + } + // Parse CEA 861 Serial Extension. + static int hdmi_edid_parse_extensions_cea(unsigned char *buf, struct hdmi_edid *pedid) + { + unsigned int ddc_offset, native_dtd_num, cur_offset = 4; + unsigned int underscan_support, baseaudio_support; + unsigned int tag, IEEEOUI = 0; + // unsigned int supports_ai, dc_48bit, dc_36bit, dc_30bit, dc_y444; + // unsigned char vic; + + if(buf == NULL) + return E_HDMI_EDID_PARAM; + + // Check ces extension version + if(buf[1] != 3) + { + hdmi_edid_error("[EDID-CEA] error version.\n"); + return E_HDMI_EDID_VERSION; + } + + ddc_offset = buf[2]; + underscan_support = (buf[3] >> 7) & 0x01; + baseaudio_support = (buf[3] >> 6) & 0x01; + pedid->ycbcr444 = (buf[3] >> 5) & 0x01; + pedid->ycbcr422 = (buf[3] >> 4) & 0x01; + native_dtd_num = buf[3] & 0x0F; + // hdmi_edid_debug("[EDID-CEA] ddc_offset %d underscan_support %d baseaudio_support %d yuv_support %d native_dtd_num %d\n", ddc_offset, underscan_support, baseaudio_support, yuv_support, native_dtd_num); + // Parse data block + while(cur_offset < ddc_offset) + { + tag = buf[cur_offset] >> 5; + switch(tag) + { + case 0x02: // Video Data Block + hdmi_edid_debug("[EDID-CEA] It is a Video Data Block.\n"); + hdmi_edid_get_cea_svd(buf + cur_offset, pedid); + break; + case 0x01: // Audio Data Block + hdmi_edid_debug("[EDID-CEA] It is a Audio Data Block.\n"); + hdmi_edid_parse_cea_sad(buf + cur_offset, pedid); + break; + case 0x04: // Speaker Allocation Data Block + hdmi_edid_debug("[EDID-CEA] It is a Speaker Allocatio Data Block.\n"); + break; + case 0x03: // Vendor Specific Data Block + hdmi_edid_debug("[EDID-CEA] It is a Vendor Specific Data Block.\n"); + + IEEEOUI = buf[cur_offset + 2 + 1]; + IEEEOUI <<= 8; + IEEEOUI += buf[cur_offset + 1 + 1]; + IEEEOUI <<= 8; + IEEEOUI += buf[cur_offset + 1]; + hdmi_edid_debug("[EDID-CEA] IEEEOUI is 0x%08x.\n", IEEEOUI); + if(IEEEOUI == 0x0c03) + pedid->sink_hdmi = 1; + // if(count > 5) + // { + // pedid->deepcolor = (buf[cur_offset + 5] >> 3) & 0x0F; + // supports_ai = buf[cur_offset + 5] >> 7; + // dc_48bit = (buf[cur_offset + 5] >> 6) & 0x1; + // dc_36bit = (buf[cur_offset + 5] >> 5) & 0x1; + // dc_30bit = (buf[cur_offset + 5] >> 4) & 0x1; + // dc_y444 = (buf[cur_offset + 5] >> 3) & 0x1; + // hdmi_edid_debug("[EDID-CEA] supports_ai %d dc_48bit %d dc_36bit %d dc_30bit %d dc_y444 %d \n", supports_ai, dc_48bit, dc_36bit, dc_30bit, dc_y444); + // } + // if(count > 6) + // pedid->maxtmdsclock = buf[cur_offset + 6] * 5000000; + // if(count > 7) + // { + // pedid->latency_fields_present = (buf[cur_offset + 7] & 0x80) ? 1:0; + // pedid->i_latency_fields_present = (buf[cur_offset + 7] & 0x40) ? 1:0; + // } + // if(count > 9 && pedid->latency_fields_present) + // { + // pedid->video_latency = buf[cur_offset + 8]; + // pedid->audio_latency = buf[cur_offset + 9]; + // } + // if(count > 11 && pedid->i_latency_fields_present) + // { + // pedid->interlaced_video_latency = buf[cur_offset + 10]; + // pedid->interlaced_audio_latency = buf[cur_offset + 11]; + // } + break; + case 0x05: // VESA DTC Data Block + hdmi_edid_debug("[EDID-CEA] It is a VESA DTC Data Block.\n"); + break; + case 0x07: // Use Extended Tag + hdmi_edid_debug("[EDID-CEA] It is a Use Extended Tag Data Block.\n"); + break; + default: + hdmi_edid_error("[EDID-CEA] unkowned data block tag.\n"); + break; + } + cur_offset += (buf[cur_offset] & 0x1F) + 1; + } + #if 1 + { + // Parse DTD + struct fb_videomode *vmode = kmalloc(sizeof(struct fb_videomode), GFP_KERNEL); + if(vmode == NULL) + return E_HDMI_EDID_SUCCESS; + while(ddc_offset < HDMI_EDID_BLOCK_SIZE - 2) //buf[126] = 0 and buf[127] = checksum + { + if(!buf[ddc_offset] && !buf[ddc_offset + 1]) + break; + memset(vmode, 0, sizeof(struct fb_videomode)); + hdmi_edid_parse_dtd(buf + ddc_offset, vmode); + hdmi_add_videomode(vmode, &pedid->modelist); + ddc_offset += 18; + } + kfree(vmode); + } + #endif + return E_HDMI_EDID_SUCCESS; + } + + static int hdmi_edid_parse_extensions(unsigned char *buf, struct hdmi_edid *pedid) + { + int rc; + + if(buf == NULL || pedid == NULL) + return E_HDMI_EDID_PARAM; + + // Checksum + rc = hdmi_edid_checksum(buf); + if( rc != E_HDMI_EDID_SUCCESS) + { + hdmi_edid_error("[EDID] extensions block checksum error\n"); + return E_HDMI_EDID_CHECKSUM; + } + + switch(buf[0]) + { + case 0xF0: + hdmi_edid_debug("[EDID-EXTEND] It is a extensions block map.\n"); + break; + case 0x02: + hdmi_edid_debug("[EDID-EXTEND] It is a CEA 861 Series Extension.\n"); + hdmi_edid_parse_extensions_cea(buf, pedid); + break; + case 0x10: + hdmi_edid_debug("[EDID-EXTEND] It is a Video Timing Block Extension.\n"); + break; + case 0x40: + hdmi_edid_debug("[EDID-EXTEND] It is a Display Information Extension.\n"); + break; + case 0x50: + hdmi_edid_debug("[EDID-EXTEND] It is a Localized String Extension.\n"); + break; + case 0x60: + hdmi_edid_debug("[EDID-EXTEND] It is a Digital Packet Video Link Extension.\n"); + break; + default: - hdmi_edid_debug("[EDID-EXTEND] Unkowned extension.\n"); - break; ++ hdmi_edid_error("[EDID-EXTEND] Unkowned extension.\n"); ++ return E_HDMI_EDID_UNKOWNDATA; + } + + return E_HDMI_EDID_SUCCESS; + } + + + int hdmi_sys_parse_edid(struct hdmi* hdmi) + { + struct hdmi_edid *pedid; + unsigned char *buff = NULL; + int rc = HDMI_ERROR_SUCESS, extendblock = 0, i; + + if(hdmi == NULL) + return HDMI_ERROR_FALSE; + + pedid = &(hdmi->edid); + memset(pedid, 0, sizeof(struct hdmi_edid)); + INIT_LIST_HEAD(&pedid->modelist); + + buff = kmalloc(HDMI_EDID_BLOCK_SIZE, GFP_KERNEL); + if(buff == NULL) + { + hdmi_dbg(hdmi->dev, "[%s] can not allocate memory for edid buff.\n", __FUNCTION__); + return -1; + } + // Read base block edid. + memset(buff, 0 , HDMI_EDID_BLOCK_SIZE); + rc = hdmi->read_edid(0, buff); + if(rc) + { + dev_err(hdmi->dev, "[HDMI] read edid base block error\n"); + goto out; + } + rc = hdmi_edid_parse_base(buff, &extendblock, pedid); + if(rc) + { + dev_err(hdmi->dev, "[HDMI] parse edid base block error\n"); + goto out; + } + for(i = 1; i < extendblock + 1; i++) + { + memset(buff, 0 , HDMI_EDID_BLOCK_SIZE); + rc = hdmi->read_edid(i, buff); + if(rc) + { + printk("[HDMI] read edid block %d error\n", i); + goto out; + } + rc = hdmi_edid_parse_extensions(buff, pedid); + if(rc) + { + dev_err(hdmi->dev, "[HDMI] parse edid block %d error\n", i); + continue; + } + } + out: + if(buff) + kfree(buff); + rc = hdmi_ouputmode_select(hdmi, rc); + return rc; + } diff --cc drivers/video/rockchip/rk_fb.c index fb1a94096c6a,2711cdcde8fc..902192ffd2d6 --- a/drivers/video/rockchip/rk_fb.c +++ b/drivers/video/rockchip/rk_fb.c @@@ -893,25 -861,13 +877,32 @@@ static int init_lcdc_device_driver(stru init_layer_par(dev_drv); init_completion(&dev_drv->frame_done); spin_lock_init(&dev_drv->cpl_lock); + mutex_init(&dev_drv->fb_win_id_mutex); - dev_drv->fb_layer_remap(dev_drv,FB_DEFAULT_ORDER); //102 ++ if (dev_drv->fb_layer_remap) ++ dev_drv->fb_layer_remap(dev_drv,FB_DEFAULT_ORDER); //102 dev_drv->first_frame = 1; return 0; } - static struct linux_logo *logo = NULL; - char fb_prepare_bmp_logo(struct fb_info *info, int rotate) + ++#ifdef CONFIG_LOGO_LINUX_BMP ++static const struct linux_logo *bmp_logo; ++static int fb_prepare_bmp_logo(struct fb_info *info, int rotate) +{ - logo = fb_find_logo(24); - if (logo == NULL) - printk("%s....%s..error\n",__FILE__,__FUNCTION__); ++ bmp_logo = fb_find_logo(24); ++ if (bmp_logo == NULL) { ++ printk("%s error\n", __func__); ++ return 0; ++ } + return 1; +} + - void fb_show_bmp_logo(struct fb_info *info, int rotate) ++static void fb_show_bmp_logo(struct fb_info *info, int rotate) +{ - char *framebase = info->screen_base; - memcpy(framebase,logo->data,(logo->width)*(logo->height)*4); - ++ memcpy(info->screen_base, bmp_logo->data, bmp_logo->width * bmp_logo->height * 4); +} ++#endif ++ int rk_fb_register(struct rk_lcdc_device_driver *dev_drv, struct rk_lcdc_device_driver *def_drv,int id) { diff --cc sound/soc/codecs/Kconfig index 48c2a165d13e,7a3904d93387..59596335c256 mode 100644,100755..100755 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@@ -426,3 -418,7 +426,7 @@@ config SND_SOC_WM200 config SND_SOC_WM9090 tristate + + config SND_SOC_RK2928 + tristate - depends on ARCH_RK2928 ++ depends on ARCH_RK2928 diff --cc sound/soc/codecs/Makefile index d8acd605e319,2e6d428b45d0..18d1fd604a67 mode 100644,100755..100755 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@@ -90,8 -89,7 +90,9 @@@ snd-soc-wm-hubs-objs := wm_hubs. snd-soc-rk1000-objs := rk1000_codec.o snd-soc-jz4740-codec-objs := jz4740.o snd-soc-rk610-objs := rk610_codec.o +snd-soc-rt3261-objs := rt3261.o rt3261-dsp.o rt3261_ioctl.o rt_codec_ioctl.o + snd-soc-rk2928-objs := rk2928_codec.o + # Amp snd-soc-lm4857-objs := lm4857.o snd-soc-max9877-objs := max9877.o @@@ -190,7 -187,8 +191,9 @@@ obj-$(CONFIG_SND_SOC_WM9712) += snd-soc obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o obj-$(CONFIG_SND_SOC_RK1000) += snd-soc-rk1000.o --obj-$(CONFIG_SND_SOC_RK610) += snd-soc-rk610.o ++obj-$(CONFIG_SND_SOC_RK610) += snd-soc-rk610.o + obj-$(CONFIG_SND_SOC_RK2928) += snd-soc-rk2928.o ++ # Amp obj-$(CONFIG_SND_SOC_LM4857) += snd-soc-lm4857.o obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o diff --cc sound/soc/rk29/Kconfig index 79a2f4eca225,1596ca660a73..6cde11914664 --- a/sound/soc/rk29/Kconfig +++ b/sound/soc/rk29/Kconfig @@@ -1,5 -1,5 +1,5 @@@ config SND_RK29_SOC - tristate "SoC Audio for the rockchip RK29/RK30 System-on-Chip" - tristate "SoC Audio for the rockchip RK29/RK30/RK31 System-on-Chip" ++ tristate "SoC Audio for the Rockchip System-on-Chip" depends on PLAT_RK && SND_SOC help Say Y or M if you want to add support for codecs attached to @@@ -186,7 -169,17 +186,17 @@@ config SND_RK29_SOC_RK61 Say Y if you want to add support for SoC audio on rockchip with the RK610(JETTA). - if SND_RK29_SOC_WM8988 || SND_RK29_SOC_RK1000 || SND_RK29_SOC_WM8994 || SND_RK29_SOC_WM8900 || SND_RK29_SOC_RT5621 || SND_RK29_SOC_RT5631 || SND_RK29_SOC_RT5625 || SND_RK29_SOC_RT3261 || SND_RK29_SOC_CS42L52 || SND_RK29_SOC_AIC3111 || SND_RK29_SOC_HDMI || SND_RK29_SOC_RK610 || SND_RK29_SOC_AIC3262 + config SND_RK_SOC_RK2928 + tristate "SoC I2S Audio support for rockchip - RK2928" + depends on SND_RK29_SOC && ARCH_RK2928 + select SND_RK29_SOC_I2S + select SND_SOC_RK2928 + select SND_RK29_CODEC_SOC_SLAVE + help + Say Y if you want to add support for SoC audio on rockchip + with the RK2928 internal codec. - -if SND_RK29_SOC_WM8988 || SND_RK29_SOC_RK1000 || SND_RK29_SOC_WM8994 || SND_RK29_SOC_WM8900 || SND_RK29_SOC_RT5621 || SND_RK29_SOC_RT5631 || SND_RK29_SOC_RT5625 || SND_RK29_SOC_CS42L52 || SND_RK29_SOC_AIC3111 || SND_RK29_SOC_HDMI || SND_RK29_SOC_RK610 || SND_RK29_SOC_AIC3262 || SND_RK_SOC_RK2928 ++ ++if SND_RK29_SOC_WM8988 || SND_RK29_SOC_RK1000 || SND_RK29_SOC_WM8994 || SND_RK29_SOC_WM8900 || SND_RK29_SOC_RT5621 || SND_RK29_SOC_RT5631 || SND_RK29_SOC_RT5625 || SND_RK29_SOC_RT3261 || SND_RK29_SOC_CS42L52 || SND_RK29_SOC_AIC3111 || SND_RK29_SOC_HDMI || SND_RK29_SOC_RK610 || SND_RK29_SOC_AIC3262 || SND_RK_SOC_RK2928 choice bool "Set i2s type" default SND_RK29_CODEC_SOC_SLAVE diff --cc sound/soc/rk29/Makefile index ad72a0288d65,cce9283a31d7..51c4a44de8b7 mode 100644,100755..100755 --- a/sound/soc/rk29/Makefile +++ b/sound/soc/rk29/Makefile @@@ -39,4 -44,5 +46,5 @@@ obj-$(CONFIG_SND_RK29_SOC_CS42L52) += s obj-$(CONFIG_SND_RK29_SOC_AIC3111) += snd-soc-aic3111.o obj-$(CONFIG_SND_RK29_SOC_AIC3262) += snd-soc-aic3262.o obj-$(CONFIG_SND_RK29_SOC_HDMI) += snd-soc-hdmi.o - obj-$(CONFIG_SND_RK29_SOC_RK610) += snd-soc-rk610.o + obj-$(CONFIG_SND_RK29_SOC_RK610) += snd-soc-rk610.o -obj-$(CONFIG_SND_RK_SOC_RK2928) += snd-soc-rk2928.o ++obj-$(CONFIG_SND_RK_SOC_RK2928) += snd-soc-rk2928.o