From: Tom Stellard <thomas.stellard@amd.com>
Date: Tue, 23 Jul 2013 01:47:46 +0000 (+0000)
Subject: R600: Expand vector FNEG
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=d7a472c9c696ebf010835d9254fb15036e558d84;p=oota-llvm.git

R600: Expand vector FNEG

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186913 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
index 2a4e44f8624..d74d9f89c37 100644
--- a/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -78,6 +78,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
   setOperationAction(ISD::LOAD, MVT::f64, Promote);
   AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
 
+  setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
+  setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
+
   setOperationAction(ISD::MUL, MVT::i64, Expand);
 
   setOperationAction(ISD::UDIV, MVT::i32, Expand);
diff --git a/test/CodeGen/R600/fneg.ll b/test/CodeGen/R600/fneg.ll
new file mode 100644
index 00000000000..b95cee36762
--- /dev/null
+++ b/test/CodeGen/R600/fneg.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+; XXX: There is a bug in the DAGCombiner that lowers fneg to XOR, this test
+; will need to be changed once it is fixed.
+
+; CHECK: @fneg_v2
+; CHECK: XOR_INT
+; CHECK: XOR_INT
+define void @fneg_v2(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
+entry:
+  %0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
+  store <2 x float> %0, <2 x float> addrspace(1)* %out
+  ret void
+}
+
+; CHECK: @fneg_v4
+; CHECK: XOR_INT
+; CHECK: XOR_INT
+; CHECK: XOR_INT
+; CHECK: XOR_INT
+define void @fneg_v4(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
+entry:
+  %0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
+  store <4 x float> %0, <4 x float> addrspace(1)* %out
+  ret void
+}