From: Daniel Sanders <daniel.sanders@imgtec.com>
Date: Tue, 12 Nov 2013 10:14:18 +0000 (+0000)
Subject: [mips][msa] Change constant used in ori tests to avoid conflict with bseti (also... 
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=d656c91aad9815eb819262e0d064df13e7fee5bd;p=oota-llvm.git

[mips][msa] Change constant used in ori tests to avoid conflict with bseti (also xori to avoid bnegi)

Upcoming commit(s) are going to add support for bseti and bnegi. This would
cause some existing tests to (correctly) change behaviour and emit a different
instruction. This patch prevents this by changing the constant used in ori and
xori tests so that they will not be matchable by the bseti and bnegi patterns
when these instructions are matchable from normal IR.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194467 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/Mips/msa/bitwise.ll b/test/CodeGen/Mips/msa/bitwise.ll
index 1ec373bf8c7..48e3db1df91 100644
--- a/test/CodeGen/Mips/msa/bitwise.ll
+++ b/test/CodeGen/Mips/msa/bitwise.ll
@@ -192,8 +192,8 @@ define void @or_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 
   %1 = load <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = or <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
-  ; CHECK-DAG: ori.b [[R4:\$w[0-9]+]], [[R1]], 1
+  %2 = or <16 x i8> %1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ; CHECK-DAG: ori.b [[R4:\$w[0-9]+]], [[R1]], 3
   store <16 x i8> %2, <16 x i8>* %c
   ; CHECK-DAG: st.b [[R4]], 0($4)
 
@@ -206,8 +206,8 @@ define void @or_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 
   %1 = load <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = or <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
-  ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
+  %2 = or <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 3
   ; CHECK-DAG: or.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
   store <8 x i16> %2, <8 x i16>* %c
   ; CHECK-DAG: st.h [[R4]], 0($4)
@@ -221,8 +221,8 @@ define void @or_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 
   %1 = load <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = or <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
-  ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
+  %2 = or <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
+  ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 3
   ; CHECK-DAG: or.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
   store <4 x i32> %2, <4 x i32>* %c
   ; CHECK-DAG: st.w [[R4]], 0($4)
@@ -236,8 +236,8 @@ define void @or_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 
   %1 = load <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = or <2 x i64> %1, <i64 1, i64 1>
-  ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
+  %2 = or <2 x i64> %1, <i64 3, i64 3>
+  ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 3
   ; CHECK-DAG: or.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
   store <2 x i64> %2, <2 x i64>* %c
   ; CHECK-DAG: st.d [[R4]], 0($4)
@@ -446,8 +446,8 @@ define void @xor_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
 
   %1 = load <16 x i8>* %a
   ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
-  %2 = xor <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
-  ; CHECK-DAG: xori.b [[R4:\$w[0-9]+]], [[R1]], 1
+  %2 = xor <16 x i8> %1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ; CHECK-DAG: xori.b [[R4:\$w[0-9]+]], [[R1]], 3
   store <16 x i8> %2, <16 x i8>* %c
   ; CHECK-DAG: st.b [[R4]], 0($4)
 
@@ -460,8 +460,8 @@ define void @xor_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
 
   %1 = load <8 x i16>* %a
   ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
-  %2 = xor <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
-  ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
+  %2 = xor <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 3
   ; CHECK-DAG: xor.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
   store <8 x i16> %2, <8 x i16>* %c
   ; CHECK-DAG: st.h [[R4]], 0($4)
@@ -475,8 +475,8 @@ define void @xor_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
 
   %1 = load <4 x i32>* %a
   ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
-  %2 = xor <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
-  ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
+  %2 = xor <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
+  ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 3
   ; CHECK-DAG: xor.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
   store <4 x i32> %2, <4 x i32>* %c
   ; CHECK-DAG: st.w [[R4]], 0($4)
@@ -490,8 +490,8 @@ define void @xor_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 
   %1 = load <2 x i64>* %a
   ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
-  %2 = xor <2 x i64> %1, <i64 1, i64 1>
-  ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
+  %2 = xor <2 x i64> %1, <i64 3, i64 3>
+  ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 3
   ; CHECK-DAG: xor.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
   store <2 x i64> %2, <2 x i64>* %c
   ; CHECK-DAG: st.d [[R4]], 0($4)