From: Evan Cheng <evan.cheng@apple.com>
Date: Thu, 2 May 2013 02:07:32 +0000 (+0000)
Subject: TiedTo flag can now be placed on implicit operands. isTwoAddrUse() should look
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=d4201b6e76bad9cb3fb8a20e3c04555d97deb0fd;p=oota-llvm.git

TiedTo flag can now be placed on implicit operands. isTwoAddrUse() should look
at all of the operands. Previously it was skipping over implicit operands which
cause infinite looping when the two-address pass try to reschedule a
two-address instruction below the kill of tied operand.

I'm unable to come up with a reasonably sized test case.
rdar://13747577


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180906 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 3614bdb7bbd..7ca2beef651 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -62,7 +62,8 @@ STATISTIC(NumReSchedDowns,     "Number of instructions re-scheduled down");
 // Temporary flag to disable rescheduling.
 static cl::opt<bool>
 EnableRescheduling("twoaddr-reschedule",
-                   cl::desc("Coalesce copies by rescheduling (default=true)"), cl::init(true), cl::Hidden);
+                   cl::desc("Coalesce copies by rescheduling (default=true)"),
+                   cl::init(true), cl::Hidden);
 
 namespace {
 class TwoAddressInstructionPass : public MachineFunctionPass {
@@ -432,10 +433,7 @@ static bool isKilled(MachineInstr &MI, unsigned Reg,
 /// isTwoAddrUse - Return true if the specified MI uses the specified register
 /// as a two-address use. If so, return the destination register by reference.
 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
-  const MCInstrDesc &MCID = MI.getDesc();
-  unsigned NumOps = MI.isInlineAsm()
-    ? MI.getNumOperands() : MCID.getNumOperands();
-  for (unsigned i = 0; i != NumOps; ++i) {
+  for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
     const MachineOperand &MO = MI.getOperand(i);
     if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
       continue;