From: Kevin Enderby <enderby@apple.com>
Date: Wed, 2 Mar 2011 23:08:33 +0000 (+0000)
Subject: Fixes an assertion failure while disassembling ARM rsbs reg/reg form.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=d39647d9130a52beb80bdc9116cb0f3a8affe12f;p=oota-llvm.git

Fixes an assertion failure while disassembling ARM rsbs reg/reg form.
Patch by Ted Kremenek!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126895 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 6e3fe2e039f..173275b084d 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -2203,6 +2203,19 @@ def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
   let Inst{19-16} = Rn;
   let Inst{11-0} = imm;
 }
+def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
+                 IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
+                 [/* For disassembly only; pattern left blank */]> {
+  bits<4> Rd;
+  bits<4> Rn;
+  bits<4> Rm;
+  let Inst{11-4} = 0b00000000;
+  let Inst{25} = 0;
+  let Inst{20} = 1;
+  let Inst{3-0} = Rm;
+  let Inst{15-12} = Rd;
+  let Inst{19-16} = Rn;
+}
 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
                  DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
                  [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt
index 0f6aeb7052b..0ff1e56fa4e 100644
--- a/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/test/MC/Disassembler/ARM/arm-tests.txt
@@ -130,3 +130,6 @@
 
 # CHECK: msr cpsr_fc, r0
 0x00 0xf0 0x29 0xe1
+
+# CHECK: rsbs r6, r7, r8
+0x08 0x60 0x77 0xe0