From: Jim Grosbach <grosbach@apple.com>
Date: Fri, 24 Feb 2012 00:53:11 +0000 (+0000)
Subject: Make sure the regs are low regs for tMUL size reduction.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=d1b220a33b16d97ef4194b4da625ba1c57974dee;p=oota-llvm.git

Make sure the regs are low regs for tMUL size reduction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151318 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/Thumb2SizeReduction.cpp b/lib/Target/ARM/Thumb2SizeReduction.cpp
index 776d0eff5e1..5ee5f4202ef 100644
--- a/lib/Target/ARM/Thumb2SizeReduction.cpp
+++ b/lib/Target/ARM/Thumb2SizeReduction.cpp
@@ -599,7 +599,12 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
   unsigned Reg1 = MI->getOperand(1).getReg();
   // t2MUL is "special". The tied source operand is second, not first.
   if (MI->getOpcode() == ARM::t2MUL) {
-    if (Reg0 != MI->getOperand(2).getReg()) {
+    unsigned Reg2 = MI->getOperand(2).getReg();
+    // Early exit if the regs aren't all low regs.
+    if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
+        || !isARMLowRegister(Reg2))
+      return false;
+    if (Reg0 != Reg2) {
       // If the other operand also isn't the same as the destination, we
       // can't reduce.
       if (Reg1 != Reg0)