From: Andrew Trick <atrick@apple.com>
Date: Wed, 1 Jun 2011 03:27:56 +0000 (+0000)
Subject: Add an issue width check to the postRA scheduler. Patch by Max Kazakov!
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=cf9aa284b332bc2613def3612b80c5883d4b9985;p=oota-llvm.git

Add an issue width check to the postRA scheduler. Patch by Max Kazakov!

For targets with no itinerary (x86) it is a nop by default. For
targets with issue width already expressed in the itinerary (ARM) it
bypasses a scoreboard check but otherwise does not affect the
schedule. It does make the code more consistent and complete and
allows new targets to specify their issue width in an arbitrary way.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132385 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 34c9259d2ab..95c748cba17 100644
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -661,6 +661,12 @@ void SchedulePostRATDList::ListScheduleTopDown() {
       ScheduleNodeTopDown(FoundSUnit, CurCycle);
       HazardRec->EmitInstruction(FoundSUnit);
       CycleHasInsts = true;
+      if (HazardRec->atIssueLimit()) {
+        DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle << '\n');
+        HazardRec->AdvanceCycle();
+        ++CurCycle;
+        CycleHasInsts = false;
+      }
     } else {
       if (CycleHasInsts) {
         DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n');