From: Saleem Abdulrasool <compnerd@compnerd.org>
Date: Sat, 10 Jan 2015 02:48:25 +0000 (+0000)
Subject: tests: convert a couple of ARM relocation tests to readobj
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=cc597901e5274e8edee633ee1162e9911db67a06;p=oota-llvm.git

tests: convert a couple of ARM relocation tests to readobj

These tests are checking the relocation generation.  Use the readobj output as
it is much easier to follow when glancing over the tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225575 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/MC/ARM/reloc-abs16.s b/test/MC/ARM/reloc-abs16.s
index c3c2b497b82..90229d3c1d2 100644
--- a/test/MC/ARM/reloc-abs16.s
+++ b/test/MC/ARM/reloc-abs16.s
@@ -1,6 +1,6 @@
-@ RUN: llvm-mc -triple armv7-eabi -filetype obj -o - %s | llvm-objdump -r - \
+@ RUN: llvm-mc -triple armv7-eabi -filetype obj -o - %s | llvm-readobj -r - \
 @ RUN:     | FileCheck %s
-@ RUN: llvm-mc -triple thumbv7-eabi -filetype obj -o - %s | llvm-objdump -r - \
+@ RUN: llvm-mc -triple thumbv7-eabi -filetype obj -o - %s | llvm-readobj -r - \
 @ RUN:     | FileCheck %s
 
 	.syntax unified
@@ -8,6 +8,10 @@
 	.short abs16_0 -32768
 	.short abs16_1 +65535
 
-@ CHECK: 0 R_ARM_ABS16 abs16_0
-@ CHECK: 2 R_ARM_ABS16 abs16_1
+@ CHECK: Relocations {
+@ CHECK:   Section (2) .rel.text {
+@ CHECK:     0x0 R_ARM_ABS16 abs16_0 0x0
+@ CHECK:     0x2 R_ARM_ABS16 abs16_1 0x0
+@ CHECK:   }
+@ CHECK: }
 
diff --git a/test/MC/ARM/reloc-abs8.s b/test/MC/ARM/reloc-abs8.s
index f1d7afad1ae..7f20da9a78c 100644
--- a/test/MC/ARM/reloc-abs8.s
+++ b/test/MC/ARM/reloc-abs8.s
@@ -1,6 +1,6 @@
-@ RUN: llvm-mc -triple armv7-eabi -filetype obj -o - %s | llvm-objdump -r - \
+@ RUN: llvm-mc -triple armv7-eabi -filetype obj -o - %s | llvm-readobj -r - \
 @ RUN:     | FileCheck %s
-@ RUN: llvm-mc -triple thumbv7-eabi -filetype obj -o - %s | llvm-objdump -r - \
+@ RUN: llvm-mc -triple thumbv7-eabi -filetype obj -o - %s | llvm-readobj -r - \
 @ RUN:     | FileCheck %s
 
 	.syntax unified
@@ -8,5 +8,9 @@
 	.byte abs8_0 -128
 	.byte abs8_1 +255
 
-@ CHECK: 0 R_ARM_ABS8 abs8_0
-@ CHECK: 1 R_ARM_ABS8 abs8_1
+@ CHECK: Relocations {
+@ CHECK:   Section (2) .rel.text {
+@ CHECK:     0x0 R_ARM_ABS8 abs8_0 0x0
+@ CHECK:     0x1 R_ARM_ABS8 abs8_1 0x0
+@ CHECK:   }
+@ CHECK: }