From: Elaine Zhang <zhangqing@rock-chips.com>
Date: Mon, 25 Jul 2016 02:31:58 +0000 (+0800)
Subject: clk: rockchip: rk3399: add pll up and down when change pll freq
X-Git-Tag: firefly_0821_release~2091
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=c98c6d78734dc43dad4ebdca16f5d5470dff7c22;p=firefly-linux-kernel-4.4.55.git

clk: rockchip: rk3399: add pll up and down when change pll freq

set pll sequence:
	->set pll to slow mode or other plls
	->set pll down
	->set pll params
	->set pll up
	->wait pll lock status
	->set pll to normal mode

To slove the system error:
rockchip_rk3399_wait_pll_lock: timeout waiting for pll to lock
rockchip_rk3399_pll_set_params: pll update unsucessful,
				trying to restore old params

Change-Id: I62aecd9f292de5a3c7bcd8a87231785bf115159d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 1594a29cfa82..05b40eacaf2f 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -1056,6 +1056,11 @@ static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
 		rate_change_remuxed = 1;
 	}
 
+	/* set pll power down */
+	writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
+			     RK3399_PLLCON3_PWRDOWN, 0),
+	       pll->reg_base + RK3399_PLLCON(3));
+
 	/* update pll values */
 	writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
 						  RK3399_PLLCON0_FBDIV_SHIFT),
@@ -1079,6 +1084,11 @@ static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
 					    RK3399_PLLCON3_DSMPD_SHIFT),
 		       pll->reg_base + RK3399_PLLCON(3));
 
+	/* set pll power up */
+	writel(HIWORD_UPDATE(0,
+			     RK3399_PLLCON3_PWRDOWN, 0),
+	       pll->reg_base + RK3399_PLLCON(3));
+
 	/* wait for the pll to lock */
 	ret = rockchip_rk3399_pll_wait_lock(pll);
 	if (ret) {