From: Benjamin Kramer Date: Thu, 31 May 2012 14:34:17 +0000 (+0000) Subject: X86: Rename the CLMUL target feature to PCLMUL. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=c8e340da823e8ff10b947429ef99e34ffc3067d8;p=oota-llvm.git X86: Rename the CLMUL target feature to PCLMUL. It was renamed in gcc/gas a while ago and causes all kinds of confusion because it was named differently in llvm and clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157745 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td index 8a46223afa4..7bbb2b19033 100644 --- a/lib/Target/X86/X86.td +++ b/lib/Target/X86/X86.td @@ -86,8 +86,8 @@ def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX", def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2", "Enable AVX2 instructions", [FeatureAVX]>; -def FeatureCLMUL : SubtargetFeature<"clmul", "HasCLMUL", "true", - "Enable carry-less multiplication instructions", +def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true", + "Enable packed carry-less multiplication instructions", [FeatureSSE2]>; def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true", "Enable three-operand fused multiple-add", @@ -172,20 +172,20 @@ def : Proc<"nehalem", [FeatureSSE42, FeatureCMPXCHG16B, // Westmere is the corei3/i5/i7 path from nehalem to sandybridge def : Proc<"westmere", [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem, FeatureFastUAMem, - FeaturePOPCNT, FeatureAES, FeatureCLMUL]>; + FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>; // Sandy Bridge // SSE is not listed here since llvm treats AVX as a reimplementation of SSE, // rather than a superset. def : Proc<"corei7-avx", [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT, - FeatureAES, FeatureCLMUL]>; + FeatureAES, FeaturePCLMUL]>; // Ivy Bridge def : Proc<"core-avx-i", [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT, - FeatureAES, FeatureCLMUL, + FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>; // Haswell def : Proc<"core-avx2", [FeatureAVX2, FeatureCMPXCHG16B, FeaturePOPCNT, - FeatureAES, FeatureCLMUL, FeatureRDRAND, + FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI, FeatureBMI2, FeatureFMA3]>; @@ -220,11 +220,11 @@ def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT]>; // Bulldozer def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B, - FeatureAES, FeatureCLMUL, + FeatureAES, FeaturePCLMUL, FeatureLZCNT, FeaturePOPCNT]>; // Enhanced Bulldozer def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B, - FeatureAES, FeatureCLMUL, + FeatureAES, FeaturePCLMUL, FeatureF16C, FeatureLZCNT, FeaturePOPCNT, FeatureBMI]>; diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index 0b9ce6c5b5b..de59c47466e 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -511,16 +511,16 @@ class AESAI o, Format F, dag outs, dag ins, string asm, : Ii8, TA, Requires<[HasAES]>; -// CLMUL Instruction Templates -class CLMULIi8 o, Format F, dag outs, dag ins, string asm, +// PCLMUL Instruction Templates +class PCLMULIi8 o, Format F, dag outs, dag ins, string asm, listpattern, InstrItinClass itin = IIC_DEFAULT> : Ii8, TA, - OpSize, Requires<[HasCLMUL]>; + OpSize, Requires<[HasPCLMUL]>; -class AVXCLMULIi8 o, Format F, dag outs, dag ins, string asm, +class AVXPCLMULIi8 o, Format F, dag outs, dag ins, string asm, listpattern, InstrItinClass itin = IIC_DEFAULT> : Ii8, TA, - OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>; + OpSize, VEX_4V, Requires<[HasAVX, HasPCLMUL]>; // FMA3 Instruction Templates class FMA3 o, Format F, dag outs, dag ins, string asm, diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index e1d8ff669ac..2756a9e0680 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -519,7 +519,7 @@ def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; def HasAES : Predicate<"Subtarget->hasAES()">; -def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">; +def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; def HasFMA3 : Predicate<"Subtarget->hasFMA3()">; def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; def HasXOP : Predicate<"Subtarget->hasXOP()">; diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index f74507f024d..3963ab93e78 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -7209,17 +7209,17 @@ def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst), OpSize; //===----------------------------------------------------------------------===// -// CLMUL Instructions +// PCLMUL Instructions //===----------------------------------------------------------------------===// // AVX carry-less Multiplication instructions -def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst), +def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3), "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>; -def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst), +def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2, i8imm:$src3), "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1, @@ -7227,13 +7227,13 @@ def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst), // Carry-less Multiplication instructions let Constraints = "$src1 = $dst" in { -def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst), +def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3), "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>; -def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst), +def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2, i8imm:$src3), "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1, diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp index 3e00f50ec4f..962364bda4c 100644 --- a/lib/Target/X86/X86Subtarget.cpp +++ b/lib/Target/X86/X86Subtarget.cpp @@ -202,8 +202,8 @@ void X86Subtarget::AutoDetectSubtargetFeatures() { bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0; if ((ECX >> 1) & 0x1) { - HasCLMUL = true; - ToggleFeature(X86::FeatureCLMUL); + HasPCLMUL = true; + ToggleFeature(X86::FeaturePCLMUL); } // FMA3 autodetection is switched off until we have a special flag // in code generator @@ -328,7 +328,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU, , HasPOPCNT(false) , HasSSE4A(false) , HasAES(false) - , HasCLMUL(false) + , HasPCLMUL(false) , HasFMA3(false) , HasFMA4(false) , HasXOP(false) diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h index 766f2daccbd..544491f205d 100644 --- a/lib/Target/X86/X86Subtarget.h +++ b/lib/Target/X86/X86Subtarget.h @@ -85,8 +85,8 @@ protected: /// HasAES - Target has AES instructions bool HasAES; - /// HasCLMUL - Target has carry-less multiplication - bool HasCLMUL; + /// HasPCLMUL - Target has carry-less multiplication + bool HasPCLMUL; /// HasFMA3 - Target has 3-operand fused multiply-add bool HasFMA3; @@ -203,7 +203,7 @@ public: bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; } bool hasPOPCNT() const { return HasPOPCNT; } bool hasAES() const { return HasAES; } - bool hasCLMUL() const { return HasCLMUL; } + bool hasPCLMUL() const { return HasPCLMUL; } bool hasFMA3() const { return HasFMA3; } bool hasFMA4() const { return HasFMA4; } bool hasXOP() const { return HasXOP; }