From: Chris Lattner <sabre@nondot.org>
Date: Fri, 21 Oct 2005 21:23:25 +0000 (+0000)
Subject: add a case missing from the dag combiner that exposed the failure on
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=c8597ca6985f8de7ab4398f60b0be1e1bea3a5b9;p=oota-llvm.git

add a case missing from the dag combiner that exposed the failure on
2005-10-21-longlonggtu.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23875 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b523bce339a..3efc25aebdc 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2370,6 +2370,9 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
       // Canonicalize setgt X, Min --> setne X, Min
       if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
         return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
+      // Canonicalize setlt X, Max --> setne X, Max
+      if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
+        return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
 
       // If we have setult X, 1, turn it into seteq X, 0
       if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)