From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Wed, 10 Sep 2014 23:26:16 +0000 (+0000)
Subject: R600/SI: Report offset in correct units for st64 DS instructions
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=c8256c4dcb182bb67dab268c03cd43071eccdf5a;p=oota-llvm.git

R600/SI: Report offset in correct units for st64 DS instructions

Need to convert the 64 element offset into bytes, not just the element
size like the normal case instructions.

Noticed by inspection. This can't be hit now because
st64 instructions aren't emitted during instruction selection,
and the post-RA scheduler isn't enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217560 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
index 6875181a2e5..b103ceff103 100644
--- a/lib/Target/R600/SIInstrInfo.cpp
+++ b/lib/Target/R600/SIInstrInfo.cpp
@@ -161,6 +161,18 @@ bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
   return false;
 }
 
+static bool isStride64(unsigned Opc) {
+  switch (Opc) {
+  case AMDGPU::DS_READ2ST64_B32:
+  case AMDGPU::DS_READ2ST64_B64:
+  case AMDGPU::DS_WRITE2ST64_B32:
+  case AMDGPU::DS_WRITE2ST64_B64:
+    return true;
+  default:
+    return false;
+  }
+}
+
 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
                                        unsigned &BaseReg, unsigned &Offset,
                                        const TargetRegisterInfo *TRI) const {
@@ -203,6 +215,9 @@ bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
         EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
       }
 
+      if (isStride64(Opc))
+        EltSize *= 64;
+
       const MachineOperand *AddrReg = getNamedOperand(*LdSt,
                                                       AMDGPU::OpName::addr);
       BaseReg = AddrReg->getReg();