From: Andrew Lenharth <andrewl@lenharth.org>
Date: Sat, 2 Jul 2005 20:58:53 +0000 (+0000)
Subject: I really didn't think this was necessary.  But, Legalize wasn't running again
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=c6bead211b608c51270e821f28bb50eed71be6c9;p=oota-llvm.git

I really didn't think this was necessary.  But, Legalize wasn't running again
and legalizing the extload.  Strange.  Should fix most alpha regressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22329 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 9a2740457f0..51375c5c8ee 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1351,8 +1351,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
                                    DAG.getSrcValue(NULL));
         else {
           assert(Node->getValueType(0) == MVT::f64 && "Unexpected conversion");
-          FudgeInReg = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
-                                   CPIdx, DAG.getSrcValue(NULL), MVT::f32);
+          FudgeInReg = 
+            LegalizeOp(DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
+                                   CPIdx, DAG.getSrcValue(NULL), MVT::f32));
         }
         Result = DAG.getNode(ISD::ADD, Node->getValueType(0), Tmp1, FudgeInReg);
         break;