From: Evan Cheng <evan.cheng@apple.com>
Date: Thu, 13 May 2010 20:02:08 +0000 (+0000)
Subject: Add comment about the pseudo registers QQ, each of which is a pair of Q registers.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=c4ca40eb5e632c5700fecc12ca02064429b842b0;p=oota-llvm.git

Add comment about the pseudo registers QQ, each of which is a pair of Q registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103731 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td
index 29907caa3f9..7e17caa0986 100644
--- a/lib/Target/ARM/ARMRegisterInfo.td
+++ b/lib/Target/ARM/ARMRegisterInfo.td
@@ -108,6 +108,11 @@ def Q15 : ARMReg<15, "q15", [D30, D31]>;
 
 // Pseudo 256-bit registers to represent pairs of Q registers. These should
 // never be present in the emitted code.
+// These are used for NEON load / store instructions, e.g. vld4, vst3.
+// NOTE: It's possible to define more QQ registers since technical the
+// starting D register number doesn't have to be multiple of 4. e.g. 
+// D1, D2, D3, D4 would be a legal quad. But that would make the sub-register
+// stuffs very messy.
 def QQ0 : ARMReg<0, "qq0", [Q0,  Q1]>;
 def QQ1 : ARMReg<1, "qq1", [Q2,  Q3]>;
 def QQ2 : ARMReg<2, "qq2", [Q4,  Q5]>;