From: Andrew Trick <atrick@apple.com>
Date: Tue, 7 Aug 2012 00:25:30 +0000 (+0000)
Subject: Allow x86 subtargets to use the GenericModel defined in X86Schedule.td.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=c42a7017864fc62bfff36c1b8b7f4cd68e198861;p=oota-llvm.git

Allow x86 subtargets to use the GenericModel defined in X86Schedule.td.

This allows codegen passes to query properties like
InstrItins->SchedModel->IssueWidth. It also ensure's that
computeOperandLatency returns the X86 defaults for loads and "high
latency ops". This should have no significant impact on existing
schedulers because X86 defaults happen to be the same as global
defaults.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161370 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp
index 8c35501e8a8..ae2229827b0 100644
--- a/lib/Target/X86/X86Subtarget.cpp
+++ b/lib/Target/X86/X86Subtarget.cpp
@@ -397,10 +397,10 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
     }
   }
 
-  if (X86ProcFamily == IntelAtom) {
+  if (X86ProcFamily == IntelAtom)
     PostRAScheduler = true;
-    InstrItins = getInstrItineraryForCPU(CPUName);
-  }
+
+  InstrItins = getInstrItineraryForCPU(CPUName);
 
   // It's important to keep the MCSubtargetInfo feature bits in sync with
   // target data structure which is shared with MC code emitter, etc.