From: Chris Lattner Date: Fri, 26 Jun 2009 21:25:00 +0000 (+0000) Subject: add %rip to the GR64 register class. Lets avoid allocating it to anything though! :) X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=c4233af20079b163000ea87ec42cdf3edd0c8016;p=oota-llvm.git add %rip to the GR64 register class. Lets avoid allocating it to anything though! :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74328 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp index b180beb9d69..1b76606178f 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp @@ -658,6 +658,9 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, O << " + [.-"; PrintPICBaseSymbol(); O << ']'; + } else { + assert(MO.getTargetFlags() == X86II::MO_NO_FLAG && + "Unknown operand flag for external symbol"); } if (needCloseParen) diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index d552cb3ab8e..996baa055a2 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -439,7 +439,7 @@ def GR32 : RegisterClass<"X86", [i32], 32, def GR64 : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, - RBX, R14, R15, R12, R13, RBP, RSP]> { + RBX, R14, R15, R12, R13, RBP, RSP, RIP]> { let SubRegClassList = [GR8, GR8, GR16, GR32]; let MethodProtos = [{ iterator allocation_order_end(const MachineFunction &MF) const; @@ -453,9 +453,9 @@ def GR64 : RegisterClass<"X86", [i64], 64, if (!Subtarget.is64Bit()) return begin(); // None of these are allocatable in 32-bit. if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr? - return end()-2; // If so, don't allocate RSP or RBP + return end()-3; // If so, don't allocate RIP, RSP or RBP else - return end()-1; // If not, just don't allocate RSP + return end()-2; // If not, just don't allocate RIP or RSP } }]; }