From: Hal Finkel <hfinkel@anl.gov>
Date: Thu, 3 Sep 2015 21:12:15 +0000 (+0000)
Subject: [PowerPC] Compute the MMO offset for an unaligned load with signed arithmetic
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=c2a163944ae333419b032f04e77d93527308b46a;p=oota-llvm.git

[PowerPC] Compute the MMO offset for an unaligned load with signed arithmetic

If you compute the MMO offset using unsigned arithmetic, you end up with a
large positive offset instead of a small negative one. In theory, this could
cause bad instruction-scheduling decisions later.

I noticed this by inspection from the debug output, and using that for the
regression test is the best I can do right now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246805 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 40a80d62113..116ecb4537e 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10302,7 +10302,8 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
       // original unaligned load.
       MachineFunction &MF = DAG.getMachineFunction();
       MachineMemOperand *BaseMMO =
-        MF.getMachineMemOperand(LD->getMemOperand(), -MemVT.getStoreSize()+1,
+        MF.getMachineMemOperand(LD->getMemOperand(),
+                                -(long)MemVT.getStoreSize()+1,
                                 2*MemVT.getStoreSize()-1);
 
       // Create the new base load.
diff --git a/test/CodeGen/PowerPC/unal-vec-negarith.ll b/test/CodeGen/PowerPC/unal-vec-negarith.ll
new file mode 100644
index 00000000000..faac891f5c6
--- /dev/null
+++ b/test/CodeGen/PowerPC/unal-vec-negarith.ll
@@ -0,0 +1,17 @@
+; RUN: llc -debug-only=isel <%s >%t 2>&1 && FileCheck <%t %s
+; REQUIRES: asserts
+
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define <16 x i8> @test_l_v16i8(<16 x i8>* %p) #0 {
+entry:
+  %r = load <16 x i8>, <16 x i8>* %p, align 1
+  ret <16 x i8> %r
+
+; CHECK-NOT: v4i32,ch = llvm.ppc.altivec.lvx{{.*}}<LD31[%p+4294967281](align=1)>
+; CHECK:     v4i32,ch = llvm.ppc.altivec.lvx{{.*}}<LD31[%p+-15](align=1)>
+}
+
+attributes #0 = { nounwind "target-cpu"="pwr7" }
+