From: Bob Wilson Date: Tue, 4 Aug 2009 21:39:33 +0000 (+0000) Subject: Replace dregsingle operand modifier with explicit escaped curly brackets. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=c00479253b92dd79b0345e4229af62835533347c;p=oota-llvm.git Replace dregsingle operand modifier with explicit escaped curly brackets. For other VLDn and VSTn operations, we need to list the multiple registers explicitly anyway, so there's no point in special-casing this one usage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78109 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index f36e3269b9b..540bd2f57f9 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -142,7 +142,7 @@ def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr), // VLD1 : Vector Load (multiple single elements) class VLD1D : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr), - !strconcat(OpcodeStr, "\t${dst:dregsingle}, $addr"), + !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>; class VLD1Q : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr), @@ -164,7 +164,7 @@ def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1i>; // VST1 : Vector Store (multiple single elements) class VST1D : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src), - !strconcat(OpcodeStr, "\t${src:dregsingle}, $addr"), + !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), [(IntOp addrmode6:$addr, (Ty DPR:$src))]>; class VST1Q : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src), diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp index a326185c88a..d1bf7007187 100644 --- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp @@ -348,8 +348,6 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, O << '{' << TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi) << '}'; - } else if (Modifier && strcmp(Modifier, "dregsingle") == 0) { - O << '{' << TRI->getAsmName(Reg) << '}'; } else { O << TRI->getAsmName(Reg); }