From: Vikram S. Adve <vadve@cs.uiuc.edu>
Date: Tue, 16 Sep 2003 05:55:15 +0000 (+0000)
Subject: Add flag to control whether or not delay slots are filled during
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=bed4effb84cb0834d01f9f8b1f9e87313520335f;p=oota-llvm.git

Add flag to control whether or not delay slots are filled during
instruction scheduling (this is off by default).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8553 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp
index 00a6a557f2b..392ae04d689 100644
--- a/lib/CodeGen/InstrSched/InstrScheduling.cpp
+++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp
@@ -17,6 +17,9 @@
 
 SchedDebugLevel_t SchedDebugLevel;
 
+static cl::opt<bool> EnableFillingDelaySlots("sched-fill-delay-slots",
+              cl::desc("Fill branch delay slots during local scheduling"));
+
 static cl::opt<SchedDebugLevel_t, true>
 SDL_opt("dsched", cl::Hidden, cl::location(SchedDebugLevel),
         cl::desc("enable instruction scheduling debugging information"),
@@ -1255,7 +1258,8 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
   std::vector<SchedGraphNode*> delayNodeVec;
   const MachineInstr* brInstr = NULL;
   
-  if (termInstr->getOpcode() != Instruction::Ret)
+  if (EnableFillingDelaySlots &&
+      termInstr->getOpcode() != Instruction::Ret)
   {
     // To find instructions that need delay slots without searching the full
     // machine code, we assume that the only delayed instructions are CALLs
@@ -1285,6 +1289,8 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
   
   // Also mark delay slots for other delayed instructions to hold NOPs. 
   // Simply passing in an empty delayNodeVec will have this effect.
+  // If brInstr is not handled above (EnableFillingDelaySlots == false),
+  // brInstr will be NULL so this will handle the branch instrs. as well.
   // 
   delayNodeVec.clear();
   for (unsigned i=0; i < MBB.size(); ++i)
diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
index 00a6a557f2b..392ae04d689 100644
--- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
+++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
@@ -17,6 +17,9 @@
 
 SchedDebugLevel_t SchedDebugLevel;
 
+static cl::opt<bool> EnableFillingDelaySlots("sched-fill-delay-slots",
+              cl::desc("Fill branch delay slots during local scheduling"));
+
 static cl::opt<SchedDebugLevel_t, true>
 SDL_opt("dsched", cl::Hidden, cl::location(SchedDebugLevel),
         cl::desc("enable instruction scheduling debugging information"),
@@ -1255,7 +1258,8 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
   std::vector<SchedGraphNode*> delayNodeVec;
   const MachineInstr* brInstr = NULL;
   
-  if (termInstr->getOpcode() != Instruction::Ret)
+  if (EnableFillingDelaySlots &&
+      termInstr->getOpcode() != Instruction::Ret)
   {
     // To find instructions that need delay slots without searching the full
     // machine code, we assume that the only delayed instructions are CALLs
@@ -1285,6 +1289,8 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
   
   // Also mark delay slots for other delayed instructions to hold NOPs. 
   // Simply passing in an empty delayNodeVec will have this effect.
+  // If brInstr is not handled above (EnableFillingDelaySlots == false),
+  // brInstr will be NULL so this will handle the branch instrs. as well.
   // 
   delayNodeVec.clear();
   for (unsigned i=0; i < MBB.size(); ++i)