From: Evan Cheng <evan.cheng@apple.com>
Date: Sat, 12 Jul 2008 02:22:07 +0000 (+0000)
Subject: Typos.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=b9890ae3c35ad7d8e49261650d5b98f49f97a705;p=oota-llvm.git

Typos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53504 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 85c837ae0b0..4f79696d00c 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -1055,7 +1055,7 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
       // The live range [12, 14) are not part of the r1024 live interval since
       // it's defined by an implicit def. It will not conflicts with live
       // interval of r1025. Now suppose both registers are spilled, you can
-      // easier see a situation where both registers are reloaded before
+      // easily see a situation where both registers are reloaded before
       // the INSERT_SUBREG and both target registers that would overlap.
       HasUse = false;
 
@@ -1248,7 +1248,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
       // The live range [12, 14) are not part of the r1024 live interval since
       // it's defined by an implicit def. It will not conflicts with live
       // interval of r1025. Now suppose both registers are spilled, you can
-      // easier see a situation where both registers are reloaded before
+      // easily see a situation where both registers are reloaded before
       // the INSERT_SUBREG and both target registers that would overlap.
       continue;
     RewriteMIs.push_back(RewriteInfo(index, MI, O.isUse(), O.isDef()));