From: root <root@kevin-desktop.(none)>
Date: Wed, 21 Jul 2010 01:23:32 +0000 (+0800)
Subject: update dsp driver for clk ctrl
X-Git-Tag: firefly_0821_release~11350
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=b92004ff57e68c6b669708cb079a7245d1f11344;p=firefly-linux-kernel-4.4.55.git

update dsp driver for clk ctrl
---

diff --git a/drivers/staging/rk2818/rk2818_dsp/rk2818_dsp.c b/drivers/staging/rk2818/rk2818_dsp/rk2818_dsp.c
index 0d4a3f382815..92c7287cd11f 100755
--- a/drivers/staging/rk2818/rk2818_dsp/rk2818_dsp.c
+++ b/drivers/staging/rk2818/rk2818_dsp/rk2818_dsp.c
@@ -138,8 +138,6 @@ struct rk28dsp_inf {
 
 #define DSP_CLOCK_ENABLE()		if(!inf->clk_enabled) { clk_enable(inf->clk);  inf->clk_enabled = 1; }
 #define DSP_CLOCK_DISABLE()		if(inf->clk_enabled)  { clk_disable(inf->clk); inf->clk_enabled = 0; }
-//#define DSP_CLOCK_ENABLE()		__raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x1c) & (~0x10)) , SCU_BASE_ADDR_VA+0x1c);
-//#define DSP_CLOCK_DISABLE()		__raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x1c) | (0x02)) , SCU_BASE_ADDR_VA+0x1c);
 
 
 typedef enum _DSP_STATUS {
@@ -353,13 +351,13 @@ void dsp_powerctl(int ctl, int arg)
     {
     case DPC_NORMAL:
         {
-            /* dsp clock enable 0x12*/
-			DSP_CLOCK_ENABLE();
-
             /* dsp subsys power on 0x21*/
             __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x10) & (~0x21)) , SCU_BASE_ADDR_VA+0x10);
             mdelay(15);
 
+            /* dsp clock enable 0x12*/
+			DSP_CLOCK_ENABLE();
+
             /* dsp core & peripheral rst */
             __raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x28) | 0x02000030) , SCU_BASE_ADDR_VA+0x28);
 
@@ -446,11 +444,11 @@ static int _down_firmware(char *fwname, struct rk28dsp_inf *inf)
 
 #if CLOSE_CLK_GATE
 			/* sram dsp clock enable */
-			DSP_CLOCK_ENABLE();
+			__raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x1c) & (~0x10)) , SCU_BASE_ADDR_VA+0x1c);
 			/* dsp ahb bus clock enable*/
 			__raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x24) & (~0x04)) , SCU_BASE_ADDR_VA+0x24);
 			/* dsp clock enable 0x12*/
-			__raw_writel((__raw_readl(SCU_BASE_ADDR_VA+0x1c) & (~0x02)) , SCU_BASE_ADDR_VA+0x1c);
+			DSP_CLOCK_ENABLE();
 #endif
 	        /* change dsp & arm to normal mode */
 	        inf->dsp_status = DS_NORMAL;