From: Andrew Lenharth <andrewl@lenharth.org>
Date: Wed, 4 May 2005 19:25:37 +0000 (+0000)
Subject: fix typo
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=b5884d311672a0d84c6b2627254001b27af45e2d;p=oota-llvm.git

fix typo


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21693 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index aa4ed3b13c3..3fcba64e0de 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -82,7 +82,7 @@ namespace {
       if (!EnableAlphaCT) {
         setOperationAction(ISD::CTPOP    , MVT::i64  , Expand);
         setOperationAction(ISD::CTTZ     , MVT::i64  , Expand);
-        setOperationAction(ISD::CTTZ     , MVT::i64  , Expand);
+        setOperationAction(ISD::CTLZ     , MVT::i64  , Expand);
       }
 
       //If this didn't legalize into a div....
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index badc89f8148..7722ac21df7 100644
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -89,6 +89,11 @@ namespace {
       setOperationAction(ISD::FCOS , MVT::f32, Expand);
       setOperationAction(ISD::FSQRT, MVT::f32, Expand);
 
+      //IA64 has these, but they are not implemented
+      setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
+      setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
+      setOperationAction(ISD::CTLZ , MVT::i32  , Expand);
+
       computeRegisterProperties();
 
       addLegalFPImmediate(+0.0);
diff --git a/lib/Target/PowerPC/PPC64ISelPattern.cpp b/lib/Target/PowerPC/PPC64ISelPattern.cpp
index 25fbb98acdf..54f540fcf1e 100644
--- a/lib/Target/PowerPC/PPC64ISelPattern.cpp
+++ b/lib/Target/PowerPC/PPC64ISelPattern.cpp
@@ -71,7 +71,7 @@ namespace {
       // PowerPC has these, but they are not implemented
       setOperationAction(ISD::CTPOP, MVT::i64, Expand);
       setOperationAction(ISD::CTTZ , MVT::i64, Expand);
-      setOperationAction(ISD::CTTZ , MVT::i64, Expand);
+      setOperationAction(ISD::CTLZ , MVT::i64, Expand);
 
       setShiftAmountFlavor(Extend);   // shl X, 32 == 0
       addLegalFPImmediate(+0.0); // Necessary for FSEL
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 6ed33381f35..7faaee8464b 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -72,7 +72,7 @@ namespace {
       //PowerPC has these, but they are not implemented
       setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
       setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
-      setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
+      setOperationAction(ISD::CTLZ , MVT::i32  , Expand);
 
       setSetCCResultContents(ZeroOrOneSetCCResult);
       addLegalFPImmediate(+0.0); // Necessary for FSEL
diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index 07378427497..78561fac671 100644
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -66,7 +66,7 @@ namespace {
       setOperationAction(ISD::SREM             , MVT::f64  , Expand);
       setOperationAction(ISD::CTPOP            , MVT::i32  , Expand);
       setOperationAction(ISD::CTTZ             , MVT::i32  , Expand);
-      setOperationAction(ISD::CTTZ             , MVT::i32  , Expand);
+      setOperationAction(ISD::CTLZ             , MVT::i32  , Expand);
 
       if (!UnsafeFPMath) {
         setOperationAction(ISD::FSIN           , MVT::f64  , Expand);