From: Tom Stellard <thomas.stellard@amd.com>
Date: Mon, 24 Mar 2014 16:07:28 +0000 (+0000)
Subject: SelectionDAG: Allow promotion of SELECT nodes from float to int types
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=b15ac1b99bfeaea1e1f01fa50240282dfffcc05d;p=oota-llvm.git

SelectionDAG: Allow promotion of SELECT nodes from float to int types

And vice-versa, as long as the types are the same width.

There are a few R600 tests that will cover this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204616 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 6297774484f..74c01cae437 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3990,7 +3990,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
   }
   case ISD::SELECT: {
     unsigned ExtOp, TruncOp;
-    if (Node->getValueType(0).isVector()) {
+    if (Node->getValueType(0).isVector() ||
+        Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
       ExtOp   = ISD::BITCAST;
       TruncOp = ISD::BITCAST;
     } else if (Node->getValueType(0).isInteger()) {