From: Tilmann Scheller <t.scheller@samsung.com>
Date: Fri, 29 Aug 2014 17:02:28 +0000 (+0000)
Subject: [ARM] Add Thumb-2 code size optimization test for ASR (immediate).
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=b1424d72caf5040ce212a1935228189cba7559f3;p=oota-llvm.git

[ARM] Add Thumb-2 code size optimization test for ASR (immediate).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216744 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/ARM/thumb2-size-opt.ll b/test/CodeGen/ARM/thumb2-size-opt.ll
index 4fbafb9745e..bc7e6ef9e1a 100644
--- a/test/CodeGen/ARM/thumb2-size-opt.ll
+++ b/test/CodeGen/ARM/thumb2-size-opt.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=thumbv7-linux-gnueabihf -o - -show-mc-encoding -t2-reduce-limit2=0 %s | FileCheck %s
+; RUN: llc -mtriple=thumbv7-linux-gnueabihf -o - -show-mc-encoding -t2-reduce-limit=0 -t2-reduce-limit2=0 %s | FileCheck %s
 ; RUN: llc -mtriple=thumbv7-linux-gnueabihf -o - -show-mc-encoding %s | FileCheck %s --check-prefix=CHECK-OPT
 
 define i32 @and(i32 %a, i32 %b) nounwind readnone {
@@ -10,3 +10,11 @@ entry:
   ret i32 %and
 }
 
+define i32 @asr-imm(i32 %a) nounwind readnone {
+; CHECK-LABEL: "asr-imm":
+; CHECK: asr.w r{{[0-9]+}}, r{{[0-9]+}}, #13 @ encoding: [{{0x..,0x..,0x..,0x..}}]
+; CHECK-OPT: asrs r{{[0-7]}}, r{{[0-7]}}, #13 @ encoding: [{{0x..,0x..}}]
+entry:
+  %shr = ashr i32 %a, 13
+  ret i32 %shr
+}