From: Dan Gohman <gohman@apple.com>
Date: Mon, 24 Nov 2008 19:53:21 +0000 (+0000)
Subject: Move the scheduler constructor functions to SchedulerRegistry.h, to
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=ad38b6e4e51bcda85a0ef3e8dbabde72ca3e008f;p=oota-llvm.git

Move the scheduler constructor functions to SchedulerRegistry.h, to
simplify header dependencies for front-ends that just want to choose
a scheduler and don't need all the scheduling machinery declarations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59978 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/CodeGen/LinkAllCodegenComponents.h b/include/llvm/CodeGen/LinkAllCodegenComponents.h
index 610d66b3772..07aa8b7fab5 100644
--- a/include/llvm/CodeGen/LinkAllCodegenComponents.h
+++ b/include/llvm/CodeGen/LinkAllCodegenComponents.h
@@ -16,7 +16,7 @@
 #define LLVM_CODEGEN_LINKALLCODEGENCOMPONENTS_H
 
 #include "llvm/CodeGen/Passes.h"
-#include "llvm/CodeGen/ScheduleDAGSDNodes.h"
+#include "llvm/CodeGen/SchedulerRegistry.h"
 #include "llvm/CodeGen/GCs.h"
 
 namespace {
diff --git a/include/llvm/CodeGen/ScheduleDAGSDNodes.h b/include/llvm/CodeGen/ScheduleDAGSDNodes.h
index caa1d0a281c..e795649153d 100644
--- a/include/llvm/CodeGen/ScheduleDAGSDNodes.h
+++ b/include/llvm/CodeGen/ScheduleDAGSDNodes.h
@@ -188,46 +188,6 @@ namespace llvm {
                                 const TargetInstrDesc &II,
                                 DenseMap<SDValue, unsigned> &VRBaseMap);
   };
-
-  /// createBURRListDAGScheduler - This creates a bottom up register usage
-  /// reduction list scheduler.
-  ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
-                                          SelectionDAG *DAG,
-                                          const TargetMachine *TM,
-                                          MachineBasicBlock *BB,
-                                          bool Fast);
-  
-  /// createTDRRListDAGScheduler - This creates a top down register usage
-  /// reduction list scheduler.
-  ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
-                                          SelectionDAG *DAG,
-                                          const TargetMachine *TM,
-                                          MachineBasicBlock *BB,
-                                          bool Fast);
-  
-  /// createTDListDAGScheduler - This creates a top-down list scheduler with
-  /// a hazard recognizer.
-  ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
-                                        SelectionDAG *DAG,
-                                        const TargetMachine *TM,
-                                        MachineBasicBlock *BB,
-                                        bool Fast);
-                                        
-  /// createFastDAGScheduler - This creates a "fast" scheduler.
-  ///
-  ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS,
-                                      SelectionDAG *DAG,
-                                      const TargetMachine *TM,
-                                      MachineBasicBlock *BB,
-                                      bool Fast);
-
-  /// createDefaultScheduler - This creates an instruction scheduler appropriate
-  /// for the target.
-  ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
-                                      SelectionDAG *DAG,
-                                      const TargetMachine *TM,
-                                      MachineBasicBlock *BB,
-                                      bool Fast);
 }
 
 #endif
diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h
index 84a0fec5741..d7e39aecbd3 100644
--- a/include/llvm/CodeGen/SchedulerRegistry.h
+++ b/include/llvm/CodeGen/SchedulerRegistry.h
@@ -31,9 +31,7 @@ class SelectionDAG;
 class MachineBasicBlock;
 
 class RegisterScheduler : public MachinePassRegistryNode {
-
 public:
-
   typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, SelectionDAG*,
                                         const TargetMachine *,
                                         MachineBasicBlock*, bool);
@@ -63,9 +61,48 @@ public:
   static void setListener(MachinePassRegistryListener *L) {
     Registry.setListener(L);
   }
-  
 };
 
+/// createBURRListDAGScheduler - This creates a bottom up register usage
+/// reduction list scheduler.
+ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
+                                        SelectionDAG *DAG,
+                                        const TargetMachine *TM,
+                                        MachineBasicBlock *BB,
+                                        bool Fast);
+
+/// createTDRRListDAGScheduler - This creates a top down register usage
+/// reduction list scheduler.
+ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
+                                        SelectionDAG *DAG,
+                                        const TargetMachine *TM,
+                                        MachineBasicBlock *BB,
+                                        bool Fast);
+
+/// createTDListDAGScheduler - This creates a top-down list scheduler with
+/// a hazard recognizer.
+ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
+                                      SelectionDAG *DAG,
+                                      const TargetMachine *TM,
+                                      MachineBasicBlock *BB,
+                                      bool Fast);
+                                      
+/// createFastDAGScheduler - This creates a "fast" scheduler.
+///
+ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS,
+                                    SelectionDAG *DAG,
+                                    const TargetMachine *TM,
+                                    MachineBasicBlock *BB,
+                                    bool Fast);
+
+/// createDefaultScheduler - This creates an instruction scheduler appropriate
+/// for the target.
+ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
+                                    SelectionDAG *DAG,
+                                    const TargetMachine *TM,
+                                    MachineBasicBlock *BB,
+                                    bool Fast);
+
 } // end namespace llvm