From: Chris Lattner Date: Mon, 13 Dec 2010 03:43:57 +0000 (+0000) Subject: Fix my previous patch to handle a degenerate case that the llvm-gcc X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=abf706703fcbcde8fdc69b1bbdfb34e874813107;p=oota-llvm.git Fix my previous patch to handle a degenerate case that the llvm-gcc bootstrap buildbot tripped over. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121674 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Transforms/Utils/SimplifyCFG.cpp b/lib/Transforms/Utils/SimplifyCFG.cpp index 7f9ef7cfd20..68f6905d4b5 100644 --- a/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/lib/Transforms/Utils/SimplifyCFG.cpp @@ -1820,6 +1820,22 @@ static bool TryToSimplifyUncondBranchWithICmpInIt(ICmpInst *ICI) { return SimplifyCFG(BB) | true; } + // Ok, the block is reachable from the default dest. If the constant we're + // comparing exists in one of the other edges, then we can constant fold ICI + // and zap it. + if (SI->findCaseValue(Cst) != 0) { + Value *V; + if (ICI->getPredicate() == ICmpInst::ICMP_EQ) + V = ConstantInt::getFalse(BB->getContext()); + else + V = ConstantInt::getTrue(BB->getContext()); + + ICI->replaceAllUsesWith(V); + ICI->eraseFromParent(); + // BB is now empty, so it is likely to simplify away. + return SimplifyCFG(BB) | true; + } + // The use of the icmp has to be in the 'end' block, by the only PHI node in // the block. BasicBlock *SuccBlock = BB->getTerminator()->getSuccessor(0); diff --git a/test/Transforms/SimplifyCFG/switch_create.ll b/test/Transforms/SimplifyCFG/switch_create.ll index 89478700c05..e84bc379ee5 100644 --- a/test/Transforms/SimplifyCFG/switch_create.ll +++ b/test/Transforms/SimplifyCFG/switch_create.ll @@ -88,3 +88,26 @@ lor.end: ; preds = %lor.rhs, %lor.lhs.f ; CHECK: ] } +define i32 @test5(i8 zeroext %c) nounwind ssp noredzone { +entry: + switch i8 %c, label %lor.rhs [ + i8 62, label %lor.end + i8 34, label %lor.end + i8 92, label %lor.end + ] + +lor.rhs: ; preds = %entry + %V = icmp eq i8 %c, 92 + br label %lor.end + +lor.end: ; preds = %entry, %entry, %entry, %lor.rhs + %0 = phi i1 [ true, %entry ], [ %V, %lor.rhs ], [ true, %entry ], [ true, %entry ] + %lor.ext = zext i1 %0 to i32 + ret i32 %lor.ext +; CHECK: @test5 +; CHECK: switch i8 %c, label %lor.rhs [ +; CHECK: i8 62, label %lor.end +; CHECK: i8 34, label %lor.end +; CHECK: i8 92, label %lor.end +; CHECK: ] +}