From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Sat, 14 Feb 2015 03:40:35 +0000 (+0000)
Subject: R600/SI: Fix not encoding src2 for v_div_scale_{f32|f64}
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=abcfb2b907f228d96a5565fd51bceb914fa0d428;p=oota-llvm.git

R600/SI: Fix not encoding src2 for v_div_scale_{f32|f64}

This apparently got lost in the VI changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229230 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
index 1ce8918ac32..cb16be5f2f7 100644
--- a/lib/Target/R600/SIInstrInfo.td
+++ b/lib/Target/R600/SIInstrInfo.td
@@ -988,6 +988,19 @@ multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
   } // End sdst = SIOperand.VCC, Defs = [VCC]
 }
 
+multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
+                      list<dag> pattern, string opName, string revOp,
+                      bit HasMods = 1, bit UseFullOp = 0> {
+  def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
+
+
+  def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
+            VOP3DisableFields<1, 1, HasMods>;
+
+  def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
+            VOP3DisableFields<1, 1, HasMods>;
+}
+
 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
                      list<dag> pattern, string opName,
                      bit HasMods, bit defExec> {
@@ -1289,7 +1302,7 @@ multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
 
 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
                     string opName, list<dag> pattern> :
-  VOP3b_2_m <
+  VOP3b_3_m <
   op, (outs vrc:$vdst, SReg_64:$sdst),
       (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
            InputModsNoDefault:$src1_modifiers, arc:$src1,