From: Colin LeMahieu Date: Tue, 30 Dec 2014 17:53:54 +0000 (+0000) Subject: [Hexagon] Dropping old combine instructions without encodings. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=aa4172e1d8045101f030d95061a8608def9626a0;p=oota-llvm.git [Hexagon] Dropping old combine instructions without encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224992 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/lib/Target/Hexagon/HexagonCopyToCombine.cpp index 91850613195..1883ad8f2e5 100644 --- a/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -570,7 +570,7 @@ void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt, return; } if (LoOperand.isGlobal()) { - BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_iI_V4), DoubleDestReg) + BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg) .addImm(HiOperand.getImm()) .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(), LoOperand.getTargetFlags()); @@ -588,7 +588,7 @@ void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt, if (!isUInt<6>(LoOperand.getImm())) { assert(isInt<8>(HiOperand.getImm())); - BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_iI_V4), DoubleDestReg) + BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg) .addImm(HiOperand.getImm()) .addImm(LoOperand.getImm()); return; @@ -613,7 +613,7 @@ void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt, // Handle global. if (HiOperand.isGlobal()) { - BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ir_V4), DoubleDestReg) + BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg) .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(), HiOperand.getTargetFlags()) .addReg(LoReg, LoRegKillFlag); @@ -621,7 +621,7 @@ void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt, } // Insert new combine instruction. // DoubleRegDest = combine #HiImm, LoReg - BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ir_V4), DoubleDestReg) + BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg) .addImm(HiOperand.getImm()) .addReg(LoReg, LoRegKillFlag); } @@ -638,7 +638,7 @@ void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt, // Handle global. if (LoOperand.isGlobal()) { - BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_rI_V4), DoubleDestReg) + BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg) .addReg(HiReg, HiRegKillFlag) .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(), LoOperand.getTargetFlags()); @@ -647,7 +647,7 @@ void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt, // Insert new combine instruction. // DoubleRegDest = combine HiReg, #LoImm - BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_rI_V4), DoubleDestReg) + BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg) .addReg(HiReg, HiRegKillFlag) .addImm(LoOperand.getImm()); } diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index 1d81390fe10..a92c1a9294e 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -257,50 +257,6 @@ def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))), //===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// ALU32/PERM + -//===----------------------------------------------------------------------===// - -// Combine -// Rdd=combine(Rs, #s8) -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8, - hasSideEffects = 0, validSubTargets = HasV4SubT in -def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst), - (ins IntRegs:$src1, s8Ext:$src2), - "$dst = combine($src1, #$src2)", - []>, - Requires<[HasV4T]>; - -// Rdd=combine(#s8, Rs) -let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8, - hasSideEffects = 0, validSubTargets = HasV4SubT in -def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst), - (ins s8Ext:$src1, IntRegs:$src2), - "$dst = combine(#$src1, $src2)", - []>, - Requires<[HasV4T]>; - -def HexagonWrapperCombineRI_V4 : - SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>; -def HexagonWrapperCombineIR_V4 : - SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>; - -def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i), - (COMBINE_rI_V4 IntRegs:$r, s8ExtPred:$i)>, - Requires<[HasV4T]>; - -def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r), - (COMBINE_Ir_V4 s8ExtPred:$i, IntRegs:$r)>, - Requires<[HasV4T]>; - -let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6, - hasSideEffects = 0, validSubTargets = HasV4SubT in -def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst), - (ins s8Imm:$src1, u6Ext:$src2), - "$dst = combine(#$src1, #$src2)", - []>, - Requires<[HasV4T]>; - //===----------------------------------------------------------------------===// // ALU32/PERM + //===----------------------------------------------------------------------===// @@ -331,6 +287,39 @@ let opExtendable = 1, isCodeGenOnly = 0 in def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs), "$Rdd = combine(#$s8, $Rs)">; +def HexagonWrapperCombineRI_V4 : + SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>; +def HexagonWrapperCombineIR_V4 : + SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>; + +def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i), + (A4_combineri IntRegs:$r, s8ExtPred:$i)>, + Requires<[HasV4T]>; + +def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r), + (A4_combineir s8ExtPred:$i, IntRegs:$r)>, + Requires<[HasV4T]>; + +// A4_combineii: Set two small immediates. +let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in +def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6), + "$Rdd = combine(#$s8, #$U6)"> { + bits<5> Rdd; + bits<8> s8; + bits<6> U6; + + let IClass = 0b0111; + let Inst{27-23} = 0b11001; + let Inst{20-16} = U6{5-1}; + let Inst{13} = U6{0}; + let Inst{12-5} = s8; + let Inst{4-0} = Rdd; + } + +//===----------------------------------------------------------------------===// +// ALU32/PERM - +//===----------------------------------------------------------------------===// + //===----------------------------------------------------------------------===// // LD + //===----------------------------------------------------------------------===// @@ -502,80 +491,80 @@ def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))), // zext i1->i64 def : Pat <(i64 (zext (i1 PredRegs:$src1))), - (i64 (COMBINE_Ir_V4 0, (C2_muxii (i1 PredRegs:$src1), 1, 0)))>, + (i64 (A4_combineir 0, (C2_muxii (i1 PredRegs:$src1), 1, 0)))>, Requires<[HasV4T]>; // zext i32->i64 def : Pat <(i64 (zext (i32 IntRegs:$src1))), - (i64 (COMBINE_Ir_V4 0, (i32 IntRegs:$src1)))>, + (i64 (A4_combineir 0, (i32 IntRegs:$src1)))>, Requires<[HasV4T]>; // zext i8->i64 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)), - (i64 (COMBINE_Ir_V4 0, (L2_loadrub_io AddrFI:$src1, 0)))>, + (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>, Requires<[HasV4T]>; let AddedComplexity = 20 in def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1), s11_0ExtPred:$offset))), - (i64 (COMBINE_Ir_V4 0, (L2_loadrub_io IntRegs:$src1, + (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1, s11_0ExtPred:$offset)))>, Requires<[HasV4T]>; // zext i1->i64 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)), - (i64 (COMBINE_Ir_V4 0, (L2_loadrub_io AddrFI:$src1, 0)))>, + (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>, Requires<[HasV4T]>; let AddedComplexity = 20 in def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1), s11_0ExtPred:$offset))), - (i64 (COMBINE_Ir_V4 0, (L2_loadrub_io IntRegs:$src1, + (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1, s11_0ExtPred:$offset)))>, Requires<[HasV4T]>; // zext i16->i64 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)), - (i64 (COMBINE_Ir_V4 0, (L2_loadruh_io AddrFI:$src1, 0)))>, + (i64 (A4_combineir 0, (L2_loadruh_io AddrFI:$src1, 0)))>, Requires<[HasV4T]>; let AddedComplexity = 20 in def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1), s11_1ExtPred:$offset))), - (i64 (COMBINE_Ir_V4 0, (L2_loadruh_io IntRegs:$src1, + (i64 (A4_combineir 0, (L2_loadruh_io IntRegs:$src1, s11_1ExtPred:$offset)))>, Requires<[HasV4T]>; // anyext i16->i64 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)), - (i64 (COMBINE_Ir_V4 0, (L2_loadrh_io AddrFI:$src1, 0)))>, + (i64 (A4_combineir 0, (L2_loadrh_io AddrFI:$src1, 0)))>, Requires<[HasV4T]>; let AddedComplexity = 20 in def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1), s11_1ExtPred:$offset))), - (i64 (COMBINE_Ir_V4 0, (L2_loadrh_io IntRegs:$src1, + (i64 (A4_combineir 0, (L2_loadrh_io IntRegs:$src1, s11_1ExtPred:$offset)))>, Requires<[HasV4T]>; // zext i32->i64 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)), - (i64 (COMBINE_Ir_V4 0, (L2_loadri_io AddrFI:$src1, 0)))>, + (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>, Requires<[HasV4T]>; let AddedComplexity = 100 in def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))), - (i64 (COMBINE_Ir_V4 0, (L2_loadri_io IntRegs:$src1, + (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1, s11_2ExtPred:$offset)))>, Requires<[HasV4T]>; // anyext i32->i64 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)), - (i64 (COMBINE_Ir_V4 0, (L2_loadri_io AddrFI:$src1, 0)))>, + (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>, Requires<[HasV4T]>; let AddedComplexity = 100 in def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))), - (i64 (COMBINE_Ir_V4 0, (L2_loadri_io IntRegs:$src1, + (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1, s11_2ExtPred:$offset)))>, Requires<[HasV4T]>; @@ -3329,11 +3318,11 @@ def STriw_offset_ext_V4 : STInst<(outs), Requires<[HasV4T]>; def : Pat<(i64 (ctlz (i64 DoubleRegs:$src1))), - (i64 (COMBINE_Ir_V4 (i32 0), (i32 (CTLZ64_rr DoubleRegs:$src1))))>, + (i64 (A4_combineir (i32 0), (i32 (CTLZ64_rr DoubleRegs:$src1))))>, Requires<[HasV4T]>; def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))), - (i64 (COMBINE_Ir_V4 (i32 0), (i32 (CTTZ64_rr DoubleRegs:$src1))))>, + (i64 (A4_combineir (i32 0), (i32 (CTTZ64_rr DoubleRegs:$src1))))>, Requires<[HasV4T]>; @@ -3342,19 +3331,19 @@ def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))), // zextloadi8. let Predicates = [HasV4T], AddedComplexity = 120 in { def: Pat <(i64 (extloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), - (i64 (COMBINE_Ir_V4 0, (LDrib_abs_V4 tglobaladdr:$addr)))>; + (i64 (A4_combineir 0, (LDrib_abs_V4 tglobaladdr:$addr)))>; def: Pat <(i64 (zextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), - (i64 (COMBINE_Ir_V4 0, (LDriub_abs_V4 tglobaladdr:$addr)))>; + (i64 (A4_combineir 0, (LDriub_abs_V4 tglobaladdr:$addr)))>; def: Pat <(i64 (sextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), (i64 (A2_sxtw (LDrib_abs_V4 tglobaladdr:$addr)))>; def: Pat <(i64 (extloadi8 FoldGlobalAddr:$addr)), - (i64 (COMBINE_Ir_V4 0, (LDrib_abs_V4 FoldGlobalAddr:$addr)))>; + (i64 (A4_combineir 0, (LDrib_abs_V4 FoldGlobalAddr:$addr)))>; def: Pat <(i64 (zextloadi8 FoldGlobalAddr:$addr)), - (i64 (COMBINE_Ir_V4 0, (LDriub_abs_V4 FoldGlobalAddr:$addr)))>; + (i64 (A4_combineir 0, (LDriub_abs_V4 FoldGlobalAddr:$addr)))>; def: Pat <(i64 (sextloadi8 FoldGlobalAddr:$addr)), (i64 (A2_sxtw (LDrib_abs_V4 FoldGlobalAddr:$addr)))>; @@ -3364,11 +3353,11 @@ def: Pat <(i64 (sextloadi8 FoldGlobalAddr:$addr)), // zextloadi16. let AddedComplexity = 120 in { def: Pat <(i64 (extloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), - (i64 (COMBINE_Ir_V4 0, (LDrih_abs_V4 tglobaladdr:$addr)))>, + (i64 (A4_combineir 0, (LDrih_abs_V4 tglobaladdr:$addr)))>, Requires<[HasV4T]>; def: Pat <(i64 (zextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), - (i64 (COMBINE_Ir_V4 0, (LDriuh_abs_V4 tglobaladdr:$addr)))>, + (i64 (A4_combineir 0, (LDriuh_abs_V4 tglobaladdr:$addr)))>, Requires<[HasV4T]>; def: Pat <(i64 (sextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), @@ -3376,11 +3365,11 @@ def: Pat <(i64 (sextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), Requires<[HasV4T]>; def: Pat <(i64 (extloadi16 FoldGlobalAddr:$addr)), - (i64 (COMBINE_Ir_V4 0, (LDrih_abs_V4 FoldGlobalAddr:$addr)))>, + (i64 (A4_combineir 0, (LDrih_abs_V4 FoldGlobalAddr:$addr)))>, Requires<[HasV4T]>; def: Pat <(i64 (zextloadi16 FoldGlobalAddr:$addr)), - (i64 (COMBINE_Ir_V4 0, (LDriuh_abs_V4 FoldGlobalAddr:$addr)))>, + (i64 (A4_combineir 0, (LDriuh_abs_V4 FoldGlobalAddr:$addr)))>, Requires<[HasV4T]>; def: Pat <(i64 (sextloadi16 FoldGlobalAddr:$addr)), @@ -3392,11 +3381,11 @@ def: Pat <(i64 (sextloadi16 FoldGlobalAddr:$addr)), // zextloadi32. let AddedComplexity = 120 in { def: Pat <(i64 (extloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), - (i64 (COMBINE_Ir_V4 0, (LDriw_abs_V4 tglobaladdr:$addr)))>, + (i64 (A4_combineir 0, (LDriw_abs_V4 tglobaladdr:$addr)))>, Requires<[HasV4T]>; def: Pat <(i64 (zextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), - (i64 (COMBINE_Ir_V4 0, (LDriw_abs_V4 tglobaladdr:$addr)))>, + (i64 (A4_combineir 0, (LDriw_abs_V4 tglobaladdr:$addr)))>, Requires<[HasV4T]>; def: Pat <(i64 (sextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), @@ -3404,11 +3393,11 @@ def: Pat <(i64 (sextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), Requires<[HasV4T]>; def: Pat <(i64 (extloadi32 FoldGlobalAddr:$addr)), - (i64 (COMBINE_Ir_V4 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>, + (i64 (A4_combineir 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>, Requires<[HasV4T]>; def: Pat <(i64 (zextloadi32 FoldGlobalAddr:$addr)), - (i64 (COMBINE_Ir_V4 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>, + (i64 (A4_combineir 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>, Requires<[HasV4T]>; def: Pat <(i64 (sextloadi32 FoldGlobalAddr:$addr)), diff --git a/lib/Target/Hexagon/HexagonPeephole.cpp b/lib/Target/Hexagon/HexagonPeephole.cpp index a36efe701ba..e9b2ef6b391 100644 --- a/lib/Target/Hexagon/HexagonPeephole.cpp +++ b/lib/Target/Hexagon/HexagonPeephole.cpp @@ -152,7 +152,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { // Look for %vreg170 = COMBINE_ir_V4 (0, %vreg169) // %vreg170:DoublRegs, %vreg169:IntRegs if (!DisableOptExtTo64 && - MI->getOpcode () == Hexagon::COMBINE_Ir_V4) { + MI->getOpcode () == Hexagon::A4_combineir) { assert (MI->getNumOperands() == 3); MachineOperand &Dst = MI->getOperand(0); MachineOperand &Src1 = MI->getOperand(1);