From: Jakob Stoklund Olesen <stoklund@2pi.dk>
Date: Thu, 31 Mar 2011 18:42:43 +0000 (+0000)
Subject: Fix Mips, Sparc, and XCore tests that were dependent on register allocation.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=a6f74992441c998886bbf26696ea7ec9746df537;p=oota-llvm.git

Fix Mips, Sparc, and XCore tests that were dependent on register allocation.

Add an extra run with -regalloc=basic to keep them honest.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128654 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/Mips/2008-08-06-Alloca.ll b/test/CodeGen/Mips/2008-08-06-Alloca.ll
index 7be7974e0ff..5c55137627d 100644
--- a/test/CodeGen/Mips/2008-08-06-Alloca.ll
+++ b/test/CodeGen/Mips/2008-08-06-Alloca.ll
@@ -1,4 +1,9 @@
-; RUN: llc < %s -march=mips | grep {subu.*sp} | count 2
+; RUN: llc < %s -march=mips -regalloc=linearscan | grep {subu.*sp} | count 2
+
+; This test depends on a linearscan optimization, joining copies from reserved
+; registers.
+; After coalescing, copies from %SP remain.
+; They are handled by RALinScan::attemptTrivialCoalescing
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-unknown-psp-elf"
diff --git a/test/CodeGen/Mips/2010-07-20-Select.ll b/test/CodeGen/Mips/2010-07-20-Select.ll
index a2771499def..e5e2c547377 100644
--- a/test/CodeGen/Mips/2010-07-20-Select.ll
+++ b/test/CodeGen/Mips/2010-07-20-Select.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s
+; RUN: llc < %s -march=mips -relocation-model=static -regalloc=basic | FileCheck %s
 ; Fix PR7473
 
 define i32 @main() nounwind readnone {
@@ -9,12 +10,12 @@ entry:
   volatile store i32 0, i32* %c, align 4
   %0 = volatile load i32* %a, align 4             ; <i32> [#uses=1]
   %1 = icmp eq i32 %0, 0                          ; <i1> [#uses=1]
-; CHECK: addiu $4, $zero, 0
+; CHECK: addiu $[[R1:[0-9]+]], $zero, 0
   %iftmp.0.0 = select i1 %1, i32 3, i32 0         ; <i32> [#uses=1]
   %2 = volatile load i32* %c, align 4             ; <i32> [#uses=1]
   %3 = icmp eq i32 %2, 0                          ; <i1> [#uses=1]
-; CHECK: addiu $4, $zero, 3
-; CHECK: addu $2, $3, $4
+; CHECK: addiu $[[R1]], $zero, 3
+; CHECK: addu $2, ${{.}}, $[[R1]]
   %iftmp.2.0 = select i1 %3, i32 0, i32 5         ; <i32> [#uses=1]
   %4 = add nsw i32 %iftmp.2.0, %iftmp.0.0         ; <i32> [#uses=1]
   ret i32 %4
diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll
index 7d3e0252e3c..8329c891f0c 100755
--- a/test/CodeGen/Mips/cmov.ll
+++ b/test/CodeGen/Mips/cmov.ll
@@ -1,10 +1,11 @@
 ; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
+; RUN: llc -march=mips -mcpu=4ke -regalloc=basic < %s | FileCheck %s
 
 @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
 @i3 = common global i32* null, align 4
 
-; CHECK:  lw  $3, %got(i3)($gp)
-; CHECK:  addiu $5, $gp, %got(i1)
+; CHECK:  lw  ${{[0-9]+}}, %got(i3)($gp)
+; CHECK:  addiu ${{[0-9]+}}, $gp, %got(i1)
 define i32* @cmov1(i32 %s) nounwind readonly {
 entry:
   %tobool = icmp ne i32 %s, 0
diff --git a/test/CodeGen/Mips/o32_cc_vararg.ll b/test/CodeGen/Mips/o32_cc_vararg.ll
index 50b43b486cb..6601d250556 100644
--- a/test/CodeGen/Mips/o32_cc_vararg.ll
+++ b/test/CodeGen/Mips/o32_cc_vararg.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips2 < %s -regalloc=basic | FileCheck %s
 
 
 ; All test functions do the same thing - they return the first variable
@@ -56,14 +57,14 @@ entry:
 
 ; CHECK: va2:
 ; CHECK: addiu   $sp, $sp, -40
-; CHECK: addiu   $2, $sp, 44
+; CHECK: addiu   $[[R0:[0-9]+]], $sp, 44
 ; CHECK: sw      $5, 44($sp)
 ; CHECK: sw      $6, 48($sp)
 ; CHECK: sw      $7, 52($sp)
-; CHECK: addiu   $3, $2, 7
-; CHECK: addiu   $5, $zero, -8
-; CHECK: and     $3, $3, $5
-; CHECK: ldc1    $f0, 0($3)
+; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu   $[[R2:[0-9]+]], $zero, -8
+; CHECK: and     $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1    $f0, 0($[[R3]])
 }
 
 ; int
@@ -109,11 +110,11 @@ entry:
 ; CHECK: addiu   $sp, $sp, -48
 ; CHECK: sw      $6, 56($sp)
 ; CHECK: sw      $7, 60($sp)
-; CHECK: addiu   $3, $sp, 56
-; CHECK: addiu   $6, $3, 7
-; CHECK: addiu   $7, $zero, -8
-; CHECK: and     $2, $6, $7
-; CHECK: ldc1    $f0, 0($2)
+; CHECK: addiu   $[[R0:[0-9]+]], $sp, 56
+; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu   $[[R2:[0-9]+]], $zero, -8
+; CHECK: and     $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1    $f0, 0($[[R3]])
 }
 
 ; int
@@ -165,11 +166,11 @@ entry:
 ; CHECK: va6:
 ; CHECK: addiu   $sp, $sp, -48
 ; CHECK: sw      $7, 60($sp)
-; CHECK: addiu   $2, $sp, 60
-; CHECK: addiu   $3, $2, 7
-; CHECK: addiu   $4, $zero, -8
-; CHECK: and     $3, $3, $4
-; CHECK: ldc1    $f0, 0($3)
+; CHECK: addiu   $[[R0:[0-9]+]], $sp, 60
+; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu   $[[R2:[0-9]+]], $zero, -8
+; CHECK: and     $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1    $f0, 0($[[R3]])
 }
 
 ; int
@@ -215,11 +216,11 @@ entry:
 
 ; CHECK: va8:
 ; CHECK: addiu   $sp, $sp, -48
-; CHECK: addiu   $3, $sp, 64
-; CHECK: addiu   $4, $3, 7
-; CHECK: addiu   $5, $zero, -8
-; CHECK: and     $2, $4, $5
-; CHECK: ldc1    $f0, 0($2)
+; CHECK: addiu   $[[R0:[0-9]+]], $sp, 64
+; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu   $[[R2:[0-9]+]], $zero, -8
+; CHECK: and     $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1    $f0, 0($[[R3]])
 }
 
 ; int
@@ -269,9 +270,9 @@ entry:
 
 ; CHECK: va10:
 ; CHECK: addiu   $sp, $sp, -56
-; CHECK: addiu   $3, $sp, 76
-; CHECK: addiu   $2, $3, 7
-; CHECK: addiu   $4, $zero, -8
-; CHECK: and     $2, $2, $4
-; CHECK: ldc1    $f0, 0($2)
+; CHECK: addiu   $[[R0:[0-9]+]], $sp, 76
+; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu   $[[R2:[0-9]+]], $zero, -8
+; CHECK: and     $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1    $f0, 0($[[R3]])
 }
diff --git a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
index fbf72427056..6516b2d19e7 100644
--- a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
+++ b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
@@ -1,5 +1,7 @@
-;RUN: llc -march=sparc < %s | FileCheck %s -check-prefix=V8
-;RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9
+;RUN: llc -march=sparc -regalloc=linearscan < %s | FileCheck %s -check-prefix=V8
+;RUN: llc -march=sparc -regalloc=linearscan -mattr=v9 < %s | FileCheck %s -check-prefix=V9
+
+; These tests depend on linear scan's trivial coalescer for reserved registers.
 
 define i8* @frameaddr() nounwind readnone {
 entry:
diff --git a/test/CodeGen/XCore/mul64.ll b/test/CodeGen/XCore/mul64.ll
index 1dc94712507..77c6b426884 100644
--- a/test/CodeGen/XCore/mul64.ll
+++ b/test/CodeGen/XCore/mul64.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -march=xcore | FileCheck %s
+; RUN: llc < %s -march=xcore -regalloc=basic | FileCheck %s
 define i64 @umul_lohi(i32 %a, i32 %b) {
 entry:
 	%0 = zext i32 %a to i64
@@ -7,8 +8,8 @@ entry:
 	ret i64 %2
 }
 ; CHECK: umul_lohi:
-; CHECK: ldc r2, 0
-; CHECK-NEXT: lmul r1, r0, r1, r0, r2, r2
+; CHECK: ldc [[REG:r[0-9]+]], 0
+; CHECK-NEXT: lmul r1, r0, r1, r0, [[REG]], [[REG]]
 ; CHECK-NEXT: retsp 0
 
 define i64 @smul_lohi(i32 %a, i32 %b) {
@@ -19,11 +20,11 @@ entry:
 	ret i64 %2
 }
 ; CHECK: smul_lohi:
-; CHECK: ldc r2, 0
-; CHECK-NEXT: mov r3, r2
-; CHECK-NEXT: maccs r2, r3, r1, r0
-; CHECK-NEXT: mov r0, r3
-; CHECK-NEXT: mov r1, r2
+; CHECK: ldc
+; CHECK-NEXT: mov
+; CHECK-NEXT: maccs
+; CHECK-NEXT: mov r0,
+; CHECK-NEXT: mov r1,
 ; CHECK-NEXT: retsp 0
 
 define i64 @mul64(i64 %a, i64 %b) {
@@ -32,11 +33,11 @@ entry:
 	ret i64 %0
 }
 ; CHECK: mul64:
-; CHECK: ldc r11, 0
-; CHECK-NEXT: lmul r11, r4, r0, r2, r11, r11
-; CHECK-NEXT: mul r0, r0, r3
-; CHECK-NEXT: lmul r0, r1, r1, r2, r11, r0
-; CHECK-NEXT: mov r0, r4
+; CHECK: ldc
+; CHECK-NEXT: lmul
+; CHECK-NEXT: mul
+; CHECK-NEXT: lmul
+; CHECK-NEXT: mov r0,
 
 define i64 @mul64_2(i64 %a, i32 %b) {
 entry:
@@ -45,8 +46,8 @@ entry:
 	ret i64 %1
 }
 ; CHECK: mul64_2:
-; CHECK: ldc r3, 0
-; CHECK-NEXT: lmul r3, r0, r0, r2, r3, r3
-; CHECK-NEXT: mul r1, r1, r2
-; CHECK-NEXT: add r1, r3, r1
+; CHECK: ldc
+; CHECK-NEXT: lmul
+; CHECK-NEXT: mul
+; CHECK-NEXT: add r1,
 ; CHECK-NEXT: retsp 0