From: Nate Begeman <natebegeman@mac.com>
Date: Thu, 18 Aug 2005 18:01:39 +0000 (+0000)
Subject: Improve ISD::Constant codegen.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=a69404781344c4aee05935ee921bbf2844911bc0;p=oota-llvm.git

Improve ISD::Constant codegen.
Now for int foo() { return -1; } we generate:
_foo:
        li r3, -1
        blr

instead of
_foo:
        lis r2, -1
        ori r3, r2, 65535
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22864 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 18eaa9f0bf0..53205957955 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -277,15 +277,18 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
   case ISD::Constant: {
     assert(N->getValueType(0) == MVT::i32);
     unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
-    if ((unsigned)(short)v == v) {
+    unsigned Hi = HA16(v);
+    unsigned Lo = Lo16(v);
+    if (Hi && Lo) {
+      SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32, 
+                                            getI32Imm(v >> 16));
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
+    } else if (Lo) {
       CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v));
-      break;
     } else {
-      SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
-                                            getI32Imm(unsigned(v) >> 16));
-      CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
-      break;
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::LIS, getI32Imm(v >> 16));
     }
+    break;
   }
   case ISD::SIGN_EXTEND_INREG:
     switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
@@ -412,12 +415,13 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
                          Select(N->getOperand(1)));
     break;
   case ISD::AND: {
-    unsigned Imm, SH, MB, ME;
+    unsigned Imm;
     // If this is an and of a value rotated between 0 and 31 bits and then and'd
     // with a mask, emit rlwinm
     if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
                                                   isShiftedMask_32(~Imm))) {
       SDOperand Val;
+      unsigned SH, MB, ME;
       if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
         Val = Select(N->getOperand(0).getOperand(0));
       } else {
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 6eddcc48f1e..1ffa6dcb0e5 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -1736,7 +1736,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     assert(N.getValueType() == MVT::i32 &&
            "Only i32 constants are legal on this target!");
     int v = (int)cast<ConstantSDNode>(N)->getValue();
-    unsigned Hi = Hi16(v);
+    unsigned Hi = HA16(v);
     unsigned Lo = Lo16(v);
     if (Hi && Lo) {
       Tmp1 = MakeIntReg();